Lines Matching refs:PCIEIP_REG_PCIEEP_EQ_CTL67_L7DTP_E5

2281   #define PCIEIP_REG_PCIEEP_EQ_CTL67_L7DTP_E5                                                                (0xf<<16) // Lane 7 downstream port transmitter preset.  This field reserved if port is operating as a upstream port.