Lines Matching refs:PCIEIP_REG_PCIEEP_EQ_CTL1011_L10DRPH_E5

2315   #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L10DRPH_E5                                                            (0x7<<4) // Lane 10 downstream port receiver preset hint.  This field reserved if port is operating as a upstream port.