Lines Matching refs:MSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5

89357   #define MSEM_REG_INT_MASK_0_FOC_PRE_FETCH_FIFO_ERROR_E5                                                    (0x1<<29) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FOC_PRE_FETCH_FIFO_ERROR .