Lines Matching refs:MISCS_REG_RESET_CONFIG_POR

36706 #define MISCS_REG_RESET_CONFIG_POR                                                                           0x009044UL //Access:RW   DataWidth:0x4    // Reset configuration register. inside order of the bits is: [0] rst_n_reg_hard_misc_rbc_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [1] rst_n_hard_misc_rbc_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [2] rst_n_hard_misc_erstclk_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [3] reserved; Reset on POR reset.