qlnx/qlnxe/reg_addr.h

61258 #define BMB_REG_INT_STS_0                                                                                    0x5400c0UL //Access:R    DataWidth:0x20   // Multi Field Register.
61292   #define BMB_REG_INT_MASK_0_ADDRESS_ERROR                                                                   (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.ADDRESS_ERROR .
61294   #define BMB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT0_RLS_ERROR .
61296   #define BMB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT0_PROTOCOL_ERROR .
61298   #define BMB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR                                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT1_RLS_ERROR .
61300   #define BMB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT1_PROTOCOL_ERROR .
61302   #define BMB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR                                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT2_RLS_ERROR .
61304   #define BMB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT2_PROTOCOL_ERROR .
61306   #define BMB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR                                                               (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT3_RLS_ERROR .
61308   #define BMB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR                                                          (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT3_PROTOCOL_ERROR .
61310   #define BMB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_SOP_REQ_TC_PORT_ERROR .
61312   #define BMB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR                                                              (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC0_PROTOCOL_ERROR .
61314   #define BMB_REG_INT_MASK_0_WC1_PROTOCOL_ERROR                                                              (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC1_PROTOCOL_ERROR .
61316   #define BMB_REG_INT_MASK_0_WC2_PROTOCOL_ERROR                                                              (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC2_PROTOCOL_ERROR .
61318   #define BMB_REG_INT_MASK_0_WC3_PROTOCOL_ERROR                                                              (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC3_PROTOCOL_ERROR .
61320   #define BMB_REG_INT_MASK_0_LL_BLK_ERROR                                                                    (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.LL_BLK_ERROR .
61322   #define BMB_REG_INT_MASK_0_MAC0_FC_CNT_ERROR                                                               (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.MAC0_FC_CNT_ERROR .