Lines Matching defs:XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5

84427   #define XSEM_REG_INT_MASK_2_LOCK_RBC_REQ_CMD_RATE_ERROR_E5                                                 (0x1<<16) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_2.LOCK_RBC_REQ_CMD_RATE_ERROR .