Lines Matching defs:PSWRQ2_REG_HOQ_RAM_RD_STATUS_BB_K2

46180 #define PSWRQ2_REG_HOQ_RAM_RD_STATUS_BB_K2                                                                   0x240830UL //Access:R    DataWidth:0x1    // FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 data_rd2 and data_rd_3); when reset - still waiting for hoq ram read request to be completed).