Lines Matching defs:PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X128_K2_E5

26263 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X128_K2_E5                                                            0x000200UL //Access:RW   DataWidth:0x8    // Bit 7:5 amux_ena[2:0] Bit 4:0 amux_sel_o[4:0] For detailed description please refer to Phy User manual.