Lines Matching defs:PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_CMU_MASTER_CDN_O_K2_E5
29223 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_CMU_MASTER_CDN_O_K2_E5 (0x1<<0) // Master reset for CMU