Lines Matching defs:PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X47_K2_E5
33598 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X47_K2_E5 0x0020bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120