Lines Matching defs:PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_BLOCK_ALIGN_CTRL_O_K2_E5
34481 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_BLOCK_ALIGN_CTRL_O_K2_E5 (0x1<<6) // Disables the primary input lnX_block_align_control