Lines Matching defs:PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X214_K2_E5
34108 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X214_K2_E5 0x002358UL //Access:RW DataWidth:0x8 // Enables for various cdfe component during post txeq adaptation in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration