Lines Matching defs:PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5
33222 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_CDFE_TAP4_SHIFT_O_4_0_K2_E5 (0x1f<<3) // Shift factor CDFE TAP4 adapted value