Lines Matching defs:PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131_K2_E5
32833 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131_K2_E5 0x001a0cUL //Access:RW DataWidth:0x8 // Multi Field Register.