Lines Matching defs:PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O_K2_E5

36335   #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O_K2_E5                           (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode