Lines Matching defs:PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O_K2_E5

36235   #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O_K2_E5                        (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode