Lines Matching defs:PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5
30007 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O_K2_E5 (0x1<<1) // MSM Function RST mode default value for reset_cmu_gcrx