Lines Matching defs:PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_K2_E5

14433   #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_K2_E5                                   (0x7<<2) // Test clock divider control. This register controls a programmable divider on the test clock path before clock distribution from the CMU macro to all lanes macros.  0x0 - DIV1 0x1 - DIV2 0x2 - DIV4 0x3 - DIV5 0x4 - DIV8 0x5 - DIV10 0x6 - DIV16 0x7 - DIV20