Lines Matching defs:PCIEIP_REG_VF_BAR4_ADDRESS_BB

2878   #define PCIEIP_REG_VF_BAR4_ADDRESS_BB                                                                      (0xfffff<<12) // These bits set the address within a 32-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR5 to create a full 64 bit address decode. Only the bits that addresses blocks bigger than the setting in the VFBAR4_SIZE(reg 0x620) value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.