Lines Matching defs:PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_MDIO_RST_BB

6367   #define PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_MDIO_RST_BB                                                        (0x1<<3) // Tthis bit when set will allow bit 2 value to propogate to Serdes. This bit acts as the mux sel for a soft MDIO reset.