Lines Matching defs:PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_K2

2408   #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_K2                                                 (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset2.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R