Lines Matching defs:PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_BADSYNC_ALWAYS_BB

8322   #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_BADSYNC_ALWAYS_BB                                                (0x1<<24) // Enable the auxilliary bad sync header to be reported as an error in all cases.