Lines Matching defs:PCIEIP_REG_PCIEEP_EQ_CTL1011_L10DTP_E5

2313   #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L10DTP_E5                                                             (0xf<<0) // Lane 10 downstream port transmitter preset.  This field reserved if port is operating as a upstream port.