Lines Matching defs:MISC_REG_AEU_ENABLE9_MCP_OUT_4

36564 #define MISC_REG_AEU_ENABLE9_MCP_OUT_4                                                                       0x0086d8UL //Access:RW   DataWidth:0x20   // Nineth 32b for enabling the output for output4. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] PCIe link up; [6] PCIe hot reset; [7] YPLD Parity error; [8] YPLD Hw interrupt; [9] PTLD Parity error; [10] PTLD Hw interrupt; [11] RGFS Parity error; [12] RGFS Hw interrupt; [13] TGFS Parity error; [14] TGFS Hw interrupt; [15] RGSRC Parity error; [16] RGSRC Hw interrupt; [17] TGSRC Parity error; [18] TGSRC Hw interrupt; [31:19] reserved;