Lines Matching defs:IGU_REG_COMMAND_REG_32LSB_DATA

41829 #define IGU_REG_COMMAND_REG_32LSB_DATA                                                                       0x180840UL //Access:RW   DataWidth:0x20   // If the last command sent to the command_reg_ctrl was a read command, this register holds the 32LSB read value. If address is PBA: 32LSB of PBA register (one in each bit means PBA message wasnt sent due to mask). If address = SIMD with mask 64b/32LSB: 32 LSB of the during interrupt register (one in each bit means the appropriate SB is asserted. Every bit that is set will be masked in the mask bit register). If address = SIMD with mask 32MSB: this register will return zero. If address = SIMD without mask 64b: 32 LSB of the during interrupt register (one in each bit means the appropriate SB is asserted). If the command sent to the command_reg_ctrl is a write command the data in this register is used as follows:  If address = interrupt acknowledge register or producer update: same as Consumer & Producer update command.  If address = attention update: Attention ack new value = command_reg_32lsb_data. If address = attention set: Attention ack new value = attention ack old value | command_reg_32lsb_data. If address = attention clear: Attention ack new value = attention ack old value  & command_reg_32lsb_data.