Lines Matching refs:bank

217 	vm_offset_t bank;
239 bank = (sc->sc_bank == sc->sc_bank0) ? sc->sc_bank1 : sc->sc_bank0;
240 if (erase_bank(sc->sc_dev, (uint8_t *)bank) != 0 ||
241 write_bank(sc->sc_dev, (uint8_t *)bank, sc->sc_data) != 0) {
245 sc->sc_bank = bank;
356 wait_operation_complete_amd(uint8_t *bank)
361 if ((inb(bank) ^ inb(bank)) == 0)
367 erase_bank_amd(device_t dev, uint8_t *bank)
372 OUTB_DELAY(bank + 0x555, 0xaa);
374 OUTB_DELAY(bank + 0x2aa, 0x55);
377 OUTB_DELAY(bank + 0x555, 0x80);
378 OUTB_DELAY(bank + 0x555, 0xaa);
379 OUTB_DELAY(bank + 0x2aa, 0x55);
380 OUTB_DELAY(bank, 0x30);
382 if (wait_operation_complete_amd(bank) != 0) {
388 OUTB_DELAY(bank, 0xf0);
391 if (bank[i] != 0xff) {
400 write_bank_amd(device_t dev, uint8_t *bank, uint8_t *data)
406 OUTB_DELAY(bank + 0x555, 0xaa);
408 OUTB_DELAY(bank + 0x2aa, 0x55);
411 OUTB_DELAY(bank + 0x555, 0xa0);
412 OUTB_DELAY(bank + i, data[i]);
413 if (wait_operation_complete_amd(bank) != 0) {
420 OUTB_DELAY(bank, 0xf0);
423 if (bank[i] != data[i]) {
432 wait_operation_complete_sm(uint8_t *bank)
437 outb(bank, SM_FLASH_CMD_READ_STATUS);
438 if (inb(bank) & SM_FLASH_STATUS_DONE)
445 erase_bank_sm(device_t dev, uint8_t *bank)
449 outb(bank, SM_FLASH_CMD_ERASE_SETUP);
450 outb(bank, SM_FLASH_CMD_ERASE_CONFIRM);
452 if (wait_operation_complete_sm(bank) != 0) {
457 outb(bank, SM_FLASH_CMD_CLEAR_STATUS);
458 outb(bank, SM_FLASH_CMD_RESET);
461 if (bank[i] != 0xff) {
470 write_bank_sm(device_t dev, uint8_t *bank, uint8_t *data)
475 OUTB_DELAY(bank + i, SM_FLASH_CMD_WRITE_SETUP);
476 outb(bank + i, data[i]);
477 if (wait_operation_complete_sm(bank) != 0) {
483 outb(bank, SM_FLASH_CMD_CLEAR_STATUS);
484 outb(bank, SM_FLASH_CMD_RESET);
487 if (bank[i] != data[i]) {
496 erase_bank(device_t dev, uint8_t *bank)
502 return (erase_bank_amd(dev, bank));
504 return (erase_bank_sm(dev, bank));
508 write_bank(device_t dev, uint8_t *bank, uint8_t *data)
514 return (write_bank_amd(dev, bank, data));
516 return (write_bank_sm(dev, bank, data));