sallsdk/spc/sahw.c

574   bit32 regVal;
579   regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister );
581   SA_DBG1(("siChipResetV: signature %X V_SoftResetRegister %X\n",signature,regVal));
585     SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE 0x%X\n",regVal));
586     regVal = SPCv_Reset_Write_NormalReset;
590     SA_DBG1(("siChipResetV: SPCv load HDA 0x%X\n",regVal));
591     regVal = SPCv_Reset_Write_SoftResetHDA;
595     SA_DBG1(("siChipResetV: Invalid SIGNATURE 0x%X  regVal 0x%X  a\n",signature ,regVal));
596     regVal = 1;
600   ossaHwRegWriteExt(agRoot, PCIBAR0, V_SoftResetRegister, regVal); /* siChipResetV */
619     SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE %X\n",regVal));
621     regVal =   ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ); /* siChipResetV */
622     SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE  %X\n",regVal));
624     if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NoReset)
626       SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal));
629     if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NormalResetOccurred  )
631       SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal));
634     if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_SoftResetHDAOccurred)
636       SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_SUCCESS %X\n",regVal));
639     if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_ChipResetOccurred)
641       SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal));
644     if(regVal  == 0xFFFFFFFF)
646       SA_DBG1(("siChipResetV: SPC_HDASOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal));
661     regVal =   ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister ); /* siChipResetV */
662     SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE  0x%X\n",regVal));
664     if(regVal  == 0xFFFFFFFF)
666       SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE %X\n",regVal));
669     else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NoReset)
671       SA_DBG1(("siChipResetV:SPC_SOFT_RESET_SIGNATURE  AGSA_RC_FAILURE %X\n",regVal));
674     else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_SoftResetHDAOccurred)
676       SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE 0x%X\n",regVal));
679     else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_ChipResetOccurred)
681       SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_FAILURE 0x%X\n",regVal));
684     else if((regVal & SPCv_Reset_Read_Mask) == SPCv_Reset_Read_NormalResetOccurred  )
686       SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE AGSA_RC_SUCCESS 0x%X\n",regVal));
798     regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister );
799     SA_DBG1(("siChipResetV: Reset done 0x%X ERROR_STATE 0x%X\n",regVal,
839     bit32        regVal;
846     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
847     regVal &= ~(SPC_REG_RESET_DEVICE);
848     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siChipResetSpc */
854     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
855     regVal |= SPC_REG_RESET_DEVICE;
856     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siChipResetSpc */
932     bit32                      regVal, toggleVal;
984     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_IOP);
985     SA_DBG1(("MBIC(A) - NMI Enable VPE0 (IOP): = 0x%x\n", regVal));
999     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, MBIC_NMI_ENABLE_VPE0_AAP1);
1000     SA_DBG1(("MBIC(A) - NMI Enable VPE0 (AAP1): = 0x%x\n", regVal));
1003     regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT_ENABLE);
1004     SA_DBG1(("PCIE - Event Interrupt Enable Register: = 0x%x\n", regVal));
1007     regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT);
1008     SA_DBG1(("PCIE - Event Interrupt Register: = 0x%x\n", regVal));
1009     ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_EVENT_INTERRUPT, regVal);  /* siSpcSoftReset */
1011     regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT_ENABLE);
1012     SA_DBG1(("PCIE - Error Interrupt Enable Register: = 0x%x\n", regVal));
1015     regVal = ossaHwRegReadExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT);
1016     SA_DBG1(("PCIE - Error Interrupt Register: = 0x%x\n", regVal));
1017     ossaHwRegWriteExt(agRoot, PCIBAR1, PCIE_ERROR_INTERRUPT, regVal); /* siSpcSoftReset */
1020     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST;
1021     toggleVal = regVal ^ SCRATCH_PAD1_RST;
1045     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET);
1054     regVal &= ~(0x00003b00);
1056     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */
1104     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
1105     SA_DBG1(("GPIO Output Control Register: = 0x%x\n", regVal));
1107     regVal &= 0xFFFFFFFC;
1108     ossaHwRegWriteExt(agRoot, PCIBAR2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); /* siSpcSoftReset */
1124     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
1125     SA_DBG1(("Top Register before resetting IOP/AAP1: = 0x%x\n", regVal));
1126     regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1127     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1132     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
1133     SA_DBG1(("Top Register before resetting BDMA/OSSP: = 0x%x\n", regVal));
1134     regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
1135     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1146     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
1147     SA_DBG1(("Top Register before bringing up BDMA/OSSP: = 0x%x\n", regVal));
1148     regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
1149     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1171     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_CONFIG_RESET);
1180     regVal |= (GSM_CONFIG_RESET_VALUE);
1181     ossaHwRegWriteExt(agRoot, PCIBAR2, GSM_CONFIG_RESET, regVal); /* siSpcSoftReset */
1195     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_READ_ADDR_PARITY_CHECK); /* just for debugging */
1196     SA_DBG1(("GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n", regVal));
1201     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_ADDR_PARITY_CHECK); /* just for debugging */
1202     SA_DBG1(("GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n", regVal));
1207     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, GSM_WRITE_DATA_PARITY_CHECK); /* just for debugging */
1208     SA_DBG1(("GSM 0x700048 - Write Data Parity Check Enable = 0x%x\n", regVal));
1226     regVal = ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_RESET);
1227     SA_DBG1(("Top Register before bringing up IOP/AAP1: = 0x%x\n", regVal));
1228     regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1229     ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, regVal); /* siSpcSoftReset */
1250             regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST;
1251         } while ((regVal != toggleVal) && (max_wait_count -=WAIT_INCREMENT));
1255             regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1);
1256             SA_DBG1(("siSpcSoftReset: TIMEOUT:ToggleVal 0x%x, MSGU_SCRATCH_PAD1 = 0x%x\n", toggleVal, regVal));
1292        regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1);
1294        SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD1 = 0x%x\n", regVal));
1295        regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2);
1297        SA_DBG1(("siSpcSoftReset: SPC FW not ready SCRATCH_PAD2 = 0x%x\n", regVal));
1338     bit32 regVal;
1357         regVal = ossaHwRegReadExt(agRoot, PCIBAR0, V_MEMBASE_II_ShiftRegister);
1358       } while ((regVal != shiftValue) && (max_wait_count -= WAIT_INCREMENT));
1362         SA_DBG1(("siBar4Shift: TIMEOUT: SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", regVal));
1378         regVal = ossaHwRegReadExt(agRoot, PCIBAR1, SPC_IBW_AXI_TRANSLATION_LOW);
1379       } while ((regVal != shiftValue) && (max_wait_count -= WAIT_INCREMENT));
1383         SA_DBG1(("siBar4Shift: TIMEOUT: SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n", regVal));
1419     bit32                      regVal;
1506       regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS;
1507       if (regVal != BOOTTLOADERHDA_IDLE)
1510         SA_DBG1(("siHDAMode: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal));
1527       regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS;
1528     } while ((regVal != BOOTTLOADERHDA_IDLE) && (max_wait_count -= WAIT_INCREMENT));
1536         SA_DBG1(("siHDAMode: Reset: Step1:regVal =0x%x expect 0x%x\n",  regVal,ILAHDA_AAP1_IMG_GET ));
1543       SA_DBG1(("siHDAMode: Step1:TIMEOUT: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal));
1559     regVal = (HDA_ISTR_DONE | (bit32)flashImg.istrLen);
1560     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal);
1561     SA_DBG1(("siHDAMode: Step2:Host Scratchpad 3 (AAP1-ISTR): 0x%x\n", regVal));
1594     regVal = (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_SEQ_ID_BITS ) >> SHIFT16;
1595     regVal ++;
1596     regVal = (HDA_C_PA << SHIFT24) | (regVal << SHIFT16) | HDAC_EXEC_CMD;
1597     SA_DBG1(("siHDAMode: Step5:Execute ILA CMD: 0x%x\n", regVal));
1598     ossaHwRegWriteExt(agRoot, PCIBAR3, HDA_CMD_OFFSET1MB+HDA_CMD_CODE_OFFSET, regVal); /* Execute Command */
1611       regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS;
1612       if ((HDAR_EXEC == regVal) || (HDAR_BAD_IMG == regVal) || (HDAR_BAD_CMD == regVal))
1616     if (HDAR_BAD_IMG == regVal)
1618       SA_DBG1(("siHDAMode: Step6:BAD IMG: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal));
1622     if (HDAR_BAD_CMD == regVal)
1624       SA_DBG1(("siHDAMode: Step6:BAD IMG: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal));
1630       SA_DBG1(("siHDAMode: Step6:TIMEOUT: HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET = 0x%x\n", regVal));
1641     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1) & SCRATCH_PAD1_RST;
1642     SA_DBG1(("siHDAMode: Step7:MSG Scratchpad 1: 0x%x\n", regVal));
1648       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24;
1649     } while ((regVal != ILAHDA_AAP1_IMG_GET) && (max_wait_count -= WAIT_INCREMENT));
1657         SA_DBG1(("siHDAMode: Reset: Step7:regVal =0x%x expect 0x%x\n",  regVal,ILAHDA_AAP1_IMG_GET ));
1664       SA_DBG1(("siHDAMode: TIMEOUT: Step7:regVal =0x%x expect 0x%x\n",  regVal,ILAHDA_AAP1_IMG_GET ));
1674     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0);
1675     SA_DBG1(("siHDAMode: Step7:MSG Scratchpad 0: 0x%x\n", regVal));
1676     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) & 0x00FFFFFF;
1682     SA_DBG1(("siHDAMode: Step8:Push the AAP1 to 0x00400000 plus 0x%x\n", regVal));
1684     if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, regVal, flashImg.aap1Img, flashImg.aap1Len))
1686       SA_DBG1(("siHDAMode: Step8:Copy AAP1 array to 0x%x failed\n", regVal));
1697     regVal = (HDA_AAP1_DONE | (bit32)flashImg.aap1Len);
1698     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal);
1699     SA_DBG1(("siHDAMode: Step8:Host Scratchpad 3 (AAP1): 0x%x\n", regVal));
1711       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) >> SHIFT24;
1712     } while ((regVal != ILAHDA_IOP_IMG_GET) && (max_wait_count -= WAIT_INCREMENT));
1716       SA_DBG1(("siHDAMode: Step9:TIMEOUT:MSGU_SCRATCH_PAD_0 = 0x%x\n", regVal));
1725     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0);
1726     SA_DBG1(("siHDAMode: Step9:MSG Scratchpad 0: 0x%x\n", regVal));
1727     regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0) & HDA_GSM_OFFSET_BITS;
1735     SA_DBG1(("siHDAMode: Step10:Push the IOP to 0x00400000 plus 0x%x!\n", regVal));
1737     if (AGSA_RC_FAILURE == siBar4Cpy(agRoot, regVal, flashImg.iopImg, flashImg.iopLen))
1739       SA_DBG1(("siHDAMode: Step10:Copy IOP array to 0x%x failed\n", regVal));
1749     regVal = (HDA_IOP_DONE | (bit32)flashImg.iopLen);
1750     ossaHwRegWrite(agRoot, MSGU_HOST_SCRATCH_PAD_3, regVal);
1751     SA_DBG1(("siHDAMode: Step10:Host Scratchpad 3 (IOP): 0x%x\n", regVal));
1770       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_1);
1772       SA_DBG1(("siHDAMode: Step11:SPC FW not ready SCRATCH_PAD1 = 0x%x\n", regVal));
1773       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2);
1775       SA_DBG1(("siHDAMode: Step11:SPC FW not ready SCRATCH_PAD2 = 0x%x\n", regVal));
1777       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_0);
1778       SA_DBG1(("siHDAMode: Step11:ScratchPad0 AAP error code 0x%x\n", regVal));
1779       regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_3);
1780       SA_DBG1(("siHDAMode: Step11:ScratchPad3 IOP error code 0x%x\n", regVal));
2642   bit32 regVal;
2652   regVal = ossaHwRegRead(agRoot, MSGU_SCRATCH_PAD_2) & SCRATCH_PAD2_FWRDY_RST;
2654   if (regVal == SCRATCH_PAD2_FWRDY_RST)
2662     regVal = ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_STATUS_BITS;
2663     if (regVal == BOOTTLOADERHDA_IDLE)
2692       regVal = Scratchpad2 & SCRATCH_PAD2_FWRDY_RST;
2693       if (regVal != SCRATCH_PAD2_FWRDY_RST)