Lines Matching defs:dev
30 __FBSDID("$FreeBSD: stable/11/sys/dev/pci/pci.c 355359 2019-12-03 22:01:45Z jhb $");
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcivar.h>
64 #include <dev/pci/pci_private.h>
68 #include <dev/pci/pci_iov_private.h>
71 #include <dev/usb/controller/xhcireg.h>
72 #include <dev/usb/controller/ehcireg.h>
73 #include <dev/usb/controller/ohcireg.h>
74 #include <dev/usb/controller/uhcireg.h>
92 static int pci_porten(device_t dev);
93 static int pci_memen(device_t dev);
94 static void pci_assign_interrupt(device_t bus, device_t dev,
96 static int pci_add_map(device_t bus, device_t dev, int reg,
98 static int pci_probe(device_t dev);
102 static char *pci_describe_device(device_t dev);
114 static void pci_mask_msix(device_t dev, u_int index);
115 static void pci_unmask_msix(device_t dev, u_int index);
118 static void pci_resume_msi(device_t dev);
119 static void pci_resume_msix(device_t dev);
120 static int pci_remap_intr_method(device_t bus, device_t dev,
122 static int pci_reset_post(device_t dev, device_t child);
123 static int pci_reset_prepare(device_t dev, device_t child);
124 static int pci_reset_child(device_t dev, device_t child,
127 static int pci_get_id_method(device_t dev, device_t child,
447 return (dinfo->cfg.dev);
464 return (dinfo->cfg.dev);
479 return (dinfo->cfg.dev);
661 pci_alloc_devinfo_method(device_t dev)
801 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n",
1327 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1333 pci_read_vpd(device_get_parent(dev), cfg);
1344 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1352 pci_read_vpd(device_get_parent(dev), cfg);
1366 pci_fetch_vpd_list(device_t dev)
1368 struct pci_devinfo *dinfo = device_get_ivars(dev);
1372 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg);
1382 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg)
1422 pci_find_next_htcap_method(device_t dev, device_t child, int capability,
1463 pci_find_cap_method(device_t dev, device_t child, int capability,
1516 pci_find_next_cap_method(device_t dev, device_t child, int capability,
1543 pci_find_extcap_method(device_t dev, device_t child, int capability,
1580 pci_find_next_extcap_method(device_t dev, device_t child, int capability,
1613 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data)
1615 struct pci_devinfo *dinfo = device_get_ivars(dev);
1627 pci_enable_msix_method(device_t dev, device_t child, u_int index,
1655 pci_mask_msix(device_t dev, u_int index)
1657 struct pci_devinfo *dinfo = device_get_ivars(dev);
1674 pci_unmask_msix(device_t dev, u_int index)
1676 struct pci_devinfo *dinfo = device_get_ivars(dev);
1693 pci_pending_msix(device_t dev, u_int index)
1695 struct pci_devinfo *dinfo = device_get_ivars(dev);
1711 pci_resume_msix(device_t dev)
1713 struct pci_devinfo *dinfo = device_get_ivars(dev);
1722 pci_mask_msix(dev, i);
1730 pci_write_msix_entry(dev, i, mv->mv_address,
1732 pci_unmask_msix(dev, i);
1735 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1745 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1796 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1919 pci_remap_msix_method(device_t dev, device_t child, int count,
2000 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
2041 pci_release_msix(device_t dev, device_t child)
2080 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
2094 pci_msix_count_method(device_t dev, device_t child)
2105 pci_msix_pba_bar_method(device_t dev, device_t child)
2116 pci_msix_table_bar_method(device_t dev, device_t child)
2130 pci_ht_map_msi(device_t dev, uint64_t addr)
2132 struct pci_devinfo *dinfo = device_get_ivars(dev);
2142 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
2149 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
2155 pci_get_max_payload(device_t dev)
2157 struct pci_devinfo *dinfo = device_get_ivars(dev);
2164 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
2171 pci_get_max_read_req(device_t dev)
2173 struct pci_devinfo *dinfo = device_get_ivars(dev);
2180 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
2187 pci_set_max_read_req(device_t dev, int size)
2189 struct pci_devinfo *dinfo = device_get_ivars(dev);
2201 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
2204 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2);
2209 pcie_read_config(device_t dev, int reg, int width)
2211 struct pci_devinfo *dinfo = device_get_ivars(dev);
2221 return (pci_read_config(dev, cap + reg, width));
2225 pcie_write_config(device_t dev, int reg, uint32_t value, int width)
2227 struct pci_devinfo *dinfo = device_get_ivars(dev);
2233 pci_write_config(dev, cap + reg, value, width);
2244 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value,
2247 struct pci_devinfo *dinfo = device_get_ivars(dev);
2258 old = pci_read_config(dev, cap + reg, width);
2261 pci_write_config(dev, cap + reg, new, width);
2269 pci_enable_msi_method(device_t dev, device_t child, uint64_t address,
2297 pci_disable_msi_method(device_t dev, device_t child)
2317 pci_resume_msi(device_t dev)
2319 struct pci_devinfo *dinfo = device_get_ivars(dev);
2327 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
2330 pci_write_config(dev, msi->msi_location +
2332 pci_write_config(dev, msi->msi_location +
2335 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
2338 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
2343 pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
2345 struct pci_devinfo *dinfo = device_get_ivars(dev);
2369 dev, irq, &addr, &data);
2372 pci_disable_msi(dev);
2375 pci_enable_msi(dev, addr, data);
2392 dev, irq, &addr, &data);
2403 pci_mask_msix(dev, j);
2404 pci_enable_msix(dev, j, addr, data);
2405 pci_unmask_msix(dev, j);
2420 pci_msi_device_blacklisted(device_t dev)
2426 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI));
2439 device_t dev;
2451 dev = pci_find_bsf(0, 0, 0);
2452 if (dev != NULL)
2453 return (!pci_has_quirk(pci_get_devid(dev),
2459 dev = pci_find_bsf(0, 0, 0);
2460 if (dev != NULL)
2461 return (pci_msi_device_blacklisted(dev));
2471 pci_msix_device_blacklisted(device_t dev)
2477 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX))
2480 return (pci_msi_device_blacklisted(dev));
2491 device_t dev;
2496 dev = pci_find_bsf(0, 0, 0);
2497 if (dev != NULL && pci_has_quirk(pci_get_devid(dev),
2510 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2556 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2630 pci_release_msi_method(device_t dev, device_t child)
2638 error = pci_release_msix(dev, child);
2666 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2684 pci_msi_count_method(device_t dev, device_t child)
2732 pci_set_powerstate_method(device_t dev, device_t child, int state)
2770 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2797 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2804 pci_get_powerstate_method(device_t dev, device_t child)
2812 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2842 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2846 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2848 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2852 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2856 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2858 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2862 pci_enable_busmaster_method(device_t dev, device_t child)
2864 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2869 pci_disable_busmaster_method(device_t dev, device_t child)
2871 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2876 pci_enable_io_method(device_t dev, device_t child, int space)
2890 pci_set_command_bit(dev, child, bit);
2895 pci_disable_io_method(device_t dev, device_t child, int space)
2909 pci_clear_command_bit(dev, child, bit);
2925 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2943 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2976 pci_porten(device_t dev)
2978 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2982 pci_memen(device_t dev)
2984 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2988 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp,
3001 dinfo = device_get_ivars(dev);
3003 map = pci_read_config(dev, reg, 4);
3004 pci_write_config(dev, reg, 0xfffffffe, 4);
3005 testval = pci_read_config(dev, reg, 4);
3006 pci_write_config(dev, reg, map, 4);
3014 map = pci_read_config(dev, reg, 4);
3017 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
3024 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3025 pci_write_config(dev, PCIR_COMMAND,
3033 pci_write_config(dev, reg, 0xffffffff, 4);
3034 testval = pci_read_config(dev, reg, 4);
3036 pci_write_config(dev, reg + 4, 0xffffffff, 4);
3037 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
3045 pci_write_config(dev, reg, map, 4);
3047 pci_write_config(dev, reg + 4, map >> 32, 4);
3048 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
3057 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base)
3063 dinfo = device_get_ivars(dev);
3068 pci_write_config(dev, pm->pm_reg, base, 4);
3070 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
3071 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
3073 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
3078 pci_find_bar(device_t dev, int reg)
3083 dinfo = device_get_ivars(dev);
3092 pci_bar_enabled(device_t dev, struct pci_map *pm)
3097 dinfo = device_get_ivars(dev);
3101 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3109 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)
3114 dinfo = device_get_ivars(dev);
3134 pci_restore_bars(device_t dev)
3140 dinfo = device_get_ivars(dev);
3146 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
3148 pci_write_config(dev, pm->pm_reg + 4,
3158 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
3172 pm = pci_find_bar(dev, reg);
3179 pci_read_bar(dev, reg, &map, &testval, NULL);
3210 pm = pci_add_bar(dev, reg, map, mapsize);
3214 if (type == SYS_RES_IOPORT && !pci_porten(dev))
3216 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
3238 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
3239 pci_get_function(dev), reg);
3252 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
3253 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3255 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
3257 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
3258 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
3260 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
3263 if (type == SYS_RES_IOPORT && !pci_porten(dev))
3265 if (type == SYS_RES_MEMORY && !pci_memen(dev))
3288 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count,
3291 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR))
3301 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0,
3314 pci_disable_io(dev, type);
3318 pci_get_domain(dev), pci_get_bus(dev),
3319 pci_get_slot(dev), pci_get_function(dev), reg);
3322 pci_write_bar(dev, pm, start);
3335 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
3341 progif = pci_read_config(dev, PCIR_PROGIF, 1);
3343 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
3344 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
3346 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
3350 progif = pci_read_config(dev, PCIR_PROGIF, 1);
3353 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
3355 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
3360 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
3364 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
3368 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
3370 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
3375 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
3379 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
3382 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
3384 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
3389 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
3391 struct pci_devinfo *dinfo = device_get_ivars(dev);
3417 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
3429 pci_write_config(dev, PCIR_INTLINE, irq, 1);
3617 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg,
3647 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1);
3648 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1);
3651 switch (pci_get_devid(dev)) {
3653 sup_bus = pci_read_config(dev, 0x41, 1);
3657 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1);
3658 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3680 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1);
3704 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid,
3712 pci_get_domain(dev), pci_get_bus(dev),
3713 pci_get_slot(dev), pci_get_function(dev));
3717 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1);
3718 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1);
3722 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start,
3753 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid,
3765 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1);
3766 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1);
3768 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start,
3774 pci_ea_bei_to_rid(device_t dev, int bei)
3781 dinfo = device_get_ivars(dev);
3810 pci_ea_is_enabled(device_t dev, int rid)
3815 dinfo = device_get_ivars(dev);
3818 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid)
3826 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov)
3839 dinfo = device_get_ivars(dev);
3896 rid = pci_ea_bei_to_rid(dev, ea->eae_bei);
3916 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count,
3926 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4);
3928 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4);
3934 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4);
3940 pci_write_config(dev, rid, 0, 4);
3945 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3954 dinfo = device_get_ivars(dev);
3960 pci_add_resources_ea(bus, dev, 0);
3963 if ((pci_get_class(dev) == PCIC_STORAGE) &&
3964 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
3965 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
3966 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
3967 !pci_read_config(dev, PCIR_BAR(2), 4))) )
3968 pci_ata_maps(bus, dev, rl, force, prefetchmask);
3974 pci_ea_is_enabled(dev, PCIR_BAR(i))) {
3991 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
4000 pci_add_map(bus, dev, q->arg1, rl, force, 0);
4010 pci_assign_interrupt(bus, dev, 1);
4012 pci_assign_interrupt(bus, dev, 0);
4016 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
4017 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
4018 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
4019 xhci_early_takeover(dev);
4020 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
4021 ehci_early_takeover(dev);
4022 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
4023 ohci_early_takeover(dev);
4024 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
4025 uhci_early_takeover(dev);
4033 pci_reserve_secbus(bus, dev, cfg, rl);
4038 pci_identify_function(device_t pcib, device_t dev, int domain, int busno,
4043 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func);
4045 pci_add_child(dev, dinfo);
4051 pci_add_children(device_t dev, int domain, int busno)
4054 device_t pcib = device_get_parent(dev);
4067 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0);
4069 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev);
4088 pci_identify_function(pcib, dev, domain, busno, s, f);
4094 pci_rescan_method(device_t dev)
4097 device_t pcib = device_get_parent(dev);
4105 error = device_get_children(dev, &devlist, &devcount);
4118 sc = device_get_softc(dev);
4119 domain = pcib_get_domain(dev);
4120 busno = pcib_get_bus(dev);
4152 pci_identify_function(pcib, dev, domain, busno, s, f);
4161 device_delete_child(dev, devlist[i]);
4168 error = device_get_children(dev, &devlist, &devcount);
4211 return (vf_dinfo->cfg.dev);
4224 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo)
4232 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4236 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4239 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
4240 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
4241 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
4245 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS,
4249 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4);
4267 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4);
4269 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
4270 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
4274 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS,
4278 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4);
4287 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4);
4289 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4293 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4301 device_t dev;
4303 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1);
4304 device_set_ivars(dev, dinfo);
4306 pci_cfg_save(dev, dinfo, 0);
4307 pci_cfg_restore(dev, dinfo);
4309 pci_add_resources(bus, dev, 0, 0);
4310 pci_child_added(dinfo->cfg.dev);
4313 pci_add_child_clear_aer(dev, dinfo);
4315 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev);
4319 pci_child_added_method(device_t dev, device_t child)
4325 pci_probe(device_t dev)
4328 device_set_desc(dev, "PCI bus");
4335 pci_attach_common(device_t dev)
4346 sc = device_get_softc(dev);
4347 domain = pcib_get_domain(dev);
4348 busno = pcib_get_bus(dev);
4351 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno,
4354 device_printf(dev, "failed to allocate bus number\n");
4359 device_printf(dev, "domain=%d, physical bus=%d\n",
4363 if (device_get_devclass(device_get_parent(device_get_parent(dev))) !=
4365 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1,
4370 device_printf(dev, "Failed to create DMA tag: %d\n",
4377 sc->sc_dma_tag = bus_get_dma_tag(dev);
4382 pci_attach(device_t dev)
4386 error = pci_attach_common(dev);
4396 domain = pcib_get_domain(dev);
4397 busno = pcib_get_bus(dev);
4398 pci_add_children(dev, domain, busno);
4399 return (bus_generic_attach(dev));
4403 pci_detach(device_t dev)
4410 error = bus_generic_detach(dev);
4414 sc = device_get_softc(dev);
4415 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus);
4419 return (device_delete_children(dev));
4423 pci_set_power_child(device_t dev, device_t child, int state)
4435 pcib = device_get_parent(dev);
4443 pci_suspend_child(device_t dev, device_t child)
4457 error = bus_generic_suspend_child(dev, child);
4463 pci_set_power_child(dev, child, PCI_POWERSTATE_D3);
4469 pci_resume_child(device_t dev, device_t child)
4474 pci_set_power_child(dev, child, PCI_POWERSTATE_D0);
4481 bus_generic_resume_child(dev, child);
4487 pci_resume(device_t dev)
4492 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
4505 BUS_RESUME_CHILD(dev, child);
4518 BUS_RESUME_CHILD(dev, child);
4546 pci_driver_added(device_t dev, driver_t *driver)
4555 device_printf(dev, "driver added\n");
4556 DEVICE_IDENTIFY(driver, dev);
4557 if (device_get_children(dev, &devlist, &numdevs) != 0)
4569 pci_child_detached(dev, child);
4575 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
4586 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
4592 if (device_get_parent(child) != dev) {
4600 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
4614 error = PCIB_MAP_MSI(device_get_parent(dev),
4638 error = PCIB_MAP_MSI(device_get_parent(dev),
4668 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
4670 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
4673 (void)bus_generic_teardown_intr(dev, child, irq,
4683 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
4695 if (device_get_parent(child) != dev)
4696 return(bus_generic_teardown_intr(dev, child, irq, cookie));
4701 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
4734 error = bus_generic_teardown_intr(dev, child, irq, cookie);
4742 pci_print_child(device_t dev, device_t child)
4751 retval += bus_print_child_header(dev, child);
4756 if (device_get_flags(dev))
4757 retval += printf(" flags %#x", device_get_flags(dev));
4762 retval += bus_print_child_domain(dev, child);
4763 retval += bus_print_child_footer(dev, child);
4867 pci_probe_nomatch(device_t dev, device_t child)
4878 device_printf(dev, "<%s>", device);
4900 device_printf(dev, "<%s%s%s>",
4914 pci_child_detached(device_t dev, device_t child)
4927 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0)
4933 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
4935 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
4938 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0)
5020 pci_describe_device(device_t dev)
5042 if (vendor == pci_get_vendor(dev))
5056 if (device == pci_get_device(dev))
5060 snprintf(dp, 80, "0x%x", pci_get_device(dev));
5073 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
5164 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
5227 if (dinfo->cfg.dev)
5228 name = device_get_name(dinfo->cfg.dev);
5234 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
5247 pci_reserve_map(device_t dev, device_t child, int type, int *rid,
5297 device_printf(dev,
5306 device_printf(dev,
5332 res = resource_list_reserve(rl, dev, child, type, rid, start, end,
5361 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid,
5380 return (pci_alloc_secbus(dev, child, rid, start, end, count,
5399 pci_assign_interrupt(dev, child, 0);
5418 return (bus_generic_alloc_resource(dev, child,
5426 res = pci_reserve_map(dev, child, type, rid, start, end,
5432 return (resource_list_alloc(rl, dev, child, type, rid,
5437 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
5444 if (device_get_parent(child) != dev)
5445 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
5456 return (pci_vf_alloc_mem_resource(dev, child, rid,
5464 return (pci_alloc_multi_resource(dev, child, type, rid, start, end,
5469 pci_release_resource(device_t dev, device_t child, int type, int rid,
5476 if (device_get_parent(child) != dev)
5477 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
5490 return (pci_vf_release_mem_resource(dev, child, rid,
5509 return (bus_generic_release_resource(dev, child, type,
5516 return (resource_list_release(rl, dev, child, type, rid, r));
5520 pci_activate_resource(device_t dev, device_t child, int type, int rid,
5526 error = bus_generic_activate_resource(dev, child, type, rid, r);
5531 if (device_get_parent(child) == dev) {
5540 error = PCI_ENABLE_IO(dev, child, type);
5548 pci_deactivate_resource(device_t dev, device_t child, int type,
5554 error = bus_generic_deactivate_resource(dev, child, type, rid, r);
5559 if (device_get_parent(child) == dev) {
5569 pci_child_deleted(device_t dev, device_t child)
5601 resource_list_unreserve(rl, dev, child, rle->type,
5611 pci_delete_resource(device_t dev, device_t child, int type, int rid)
5617 if (device_get_parent(child) != dev)
5629 device_printf(dev, "delete_resource: "
5635 resource_list_unreserve(rl, dev, child, type, rid);
5641 pci_get_resource_list (device_t dev, device_t child)
5649 pci_get_dma_tag(device_t bus, device_t dev)
5657 pci_read_config_method(device_t dev, device_t child, int reg, int width)
5693 return (PCIB_READ_CONFIG(device_get_parent(dev),
5698 pci_write_config_method(device_t dev, device_t child, int reg,
5704 PCIB_WRITE_CONFIG(device_get_parent(dev),
5709 pci_child_location_str_method(device_t dev, device_t child, char *buf,
5720 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
5736 pci_assign_interrupt_method(device_t dev, device_t child)
5741 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
5746 pci_lookup(void *arg, const char *name, device_t *dev)
5752 if (*dev != NULL)
5791 *dev = pci_find_dbsf(domain, bus, slot, func);
5822 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo)
5824 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2)
5858 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo)
5860 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
5865 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
5876 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)
5877 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
5878 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
5879 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
5880 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
5881 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
5882 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
5883 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
5884 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
5887 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
5888 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
5891 pci_write_config(dev, PCIR_SECLAT_1,
5893 pci_write_config(dev, PCIR_SUBBUS_1,
5895 pci_write_config(dev, PCIR_SECBUS_1,
5897 pci_write_config(dev, PCIR_PRIBUS_1,
5899 pci_write_config(dev, PCIR_BRIDGECTL_1,
5903 pci_write_config(dev, PCIR_SECLAT_2,
5905 pci_write_config(dev, PCIR_SUBBUS_2,
5907 pci_write_config(dev, PCIR_SECBUS_2,
5909 pci_write_config(dev, PCIR_PRIBUS_2,
5911 pci_write_config(dev, PCIR_BRIDGECTL_2,
5915 pci_restore_bars(dev);
5921 pci_cfg_restore_pcie(dev, dinfo);
5923 pci_cfg_restore_pcix(dev, dinfo);
5927 pci_resume_msi(dev);
5929 pci_resume_msix(dev);
5933 pci_iov_cfg_restore(dev, dinfo);
5938 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo)
5940 #define RREG(n) pci_read_config(dev, pos + (n), 2)
5976 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo)
5978 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
5983 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
5995 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
5996 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
5997 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
5998 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
5999 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
6000 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
6001 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
6002 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
6003 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
6004 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
6005 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
6008 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
6009 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
6010 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
6011 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
6014 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6016 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6018 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6020 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6022 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6026 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6028 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6030 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6032 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6034 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6036 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2);
6037 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2);
6042 pci_cfg_save_pcie(dev, dinfo);
6045 pci_cfg_save_pcix(dev, dinfo);
6049 pci_iov_cfg_save(dev, dinfo);
6060 cls = pci_get_class(dev);
6083 ps = pci_get_powerstate(dev);
6085 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
6086 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
6087 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
6092 pci_save_state(device_t dev)
6096 dinfo = device_get_ivars(dev);
6097 pci_cfg_save(dev, dinfo, 0);
6101 pci_restore_state(device_t dev)
6105 dinfo = device_get_ivars(dev);
6106 pci_cfg_restore(dev, dinfo);
6110 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type,
6114 return (PCIB_GET_ID(device_get_parent(dev), child, type, id));
6119 pci_find_pcie_root_port(device_t dev)
6126 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class,
6127 ("%s: non-pci device %s", __func__, device_get_nameunit(dev)));
6134 bus = device_get_parent(dev);
6136 device_get_nameunit(dev)));
6154 dev = pcib;
6165 * exceeded. If dev is not a PCI-express function, this returns true.
6168 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay)
6170 struct pci_devinfo *dinfo = device_get_ivars(dev);
6178 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2);
6192 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2);
6204 pcie_get_max_completion_timeout(device_t dev)
6206 struct pci_devinfo *dinfo = device_get_ivars(dev);
6219 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) &
6223 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) &
6254 * If dev is not a PCI-express function or does not support FLR, this
6263 pcie_flr(device_t dev, u_int max_delay, bool force)
6265 struct pci_devinfo *dinfo = device_get_ivars(dev);
6274 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR))
6283 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
6284 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2);
6285 if (!pcie_wait_for_pending_transactions(dev, max_delay)) {
6287 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
6300 compl_delay = pcie_get_max_completion_timeout(dev) / 1000;
6307 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
6308 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl |
6314 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) &
6326 pci_power_reset(device_t dev)
6330 ps = pci_get_powerstate(dev);
6332 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
6333 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
6334 pci_set_powerstate(dev, ps);
6363 pci_reset_post(device_t dev, device_t child)
6366 if (dev == device_get_parent(child))
6372 pci_reset_prepare(device_t dev, device_t child)
6375 if (dev == device_get_parent(child))
6381 pci_reset_child(device_t dev, device_t child, int flags)
6385 if (dev == NULL || device_get_parent(child) != dev)
6391 error = BUS_SUSPEND_CHILD(dev, child);
6395 error = BUS_RESET_PREPARE(dev, child);
6398 BUS_RESET_POST(dev, child);
6403 BUS_RESUME_CHILD(dev, child);
6412 device_t dev;
6414 dev = dinfo->cfg.dev;
6417 dev_name = device_get_name(dev);
6419 printf(" (%s%d)", dev_name, device_get_unit(dev));
6426 device_t dev;
6432 dev = dinfo->cfg.dev;
6433 status = pci_read_config(dev, PCIR_STATUS, 2);
6442 status = pci_read_config(dev,
6450 pci_read_config(dev,
6456 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) {
6457 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
6458 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
6463 r1, pci_read_config(dev, aer +
6465 pci_read_config(dev, aer +
6467 r2, pci_read_config(dev, aer +
6469 pci_read_config(dev, aer +
6472 r1 = pci_read_config(dev, aer +
6491 device_t dev;
6495 dev = dinfo->cfg.dev;
6496 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
6498 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
6501 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0)
6503 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4);
6505 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4);
6506 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4);
6508 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4);
6514 device_t dev;
6518 dev = dinfo->cfg.dev;
6519 status1 = status = pci_read_config(dev, PCIR_STATUS, 2);
6525 pci_write_config(dev, PCIR_STATUS, status, 2);