nxge/xgehal/xgehal-fifo.c

29 #include <dev/nxge/include/xgehal-fifo.h>
45 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)userdata;
78 	if (fifo->config->alignment_size) {
79 	        status =__hal_fifo_dtr_align_alloc_map(fifo, txdp);
84 	              fifo->align_size,
93 	if (fifo->channel.dtr_init) {
94 	    fifo->channel.dtr_init(fifo, (xge_hal_dtr_h)txdp, index,
95 	           fifo->channel.userdata, XGE_HAL_CHANNEL_OC_NORMAL);
115 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)userdata;
128 	if (fifo->config->alignment_size) {
130 	        xge_os_dma_unmap(fifo->channel.pdev,
133 	               fifo->align_size,
140 	        xge_os_dma_free(fifo->channel.pdev,
142 	              fifo->align_size,
159 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
164 	hldev = (xge_hal_device_t *)fifo->channel.devh;
165 	fifo->config = &hldev->config.fifo;
166 	queue = &fifo->config->queue[attr->post_qid];
169 	xge_os_spin_lock_init(&fifo->channel.reserve_lock, hldev->pdev);
171 	xge_os_spin_lock_init_irq(&fifo->channel.reserve_lock, hldev->irqh);
175 	            fifo->post_lock_ptr = &hldev->xena_post_lock;
177 	        xge_os_spin_lock_init(&fifo->channel.post_lock, hldev->pdev);
178 	            fifo->post_lock_ptr = &fifo->channel.post_lock;
182 	            fifo->post_lock_ptr = &hldev->xena_post_lock;
184 	        xge_os_spin_lock_init_irq(&fifo->channel.post_lock,
186 	            fifo->post_lock_ptr = &fifo->channel.post_lock;
190 	fifo->align_size =
191 	    fifo->config->alignment_size * fifo->config->max_aligned_frags;
196 	fifo->hw_pair =
201 	fifo->interrupt_type = XGE_HAL_TXD_INT_TYPE_UTILZ;
203 	    fifo->interrupt_type = XGE_HAL_TXD_INT_TYPE_PER_LIST;
205 	fifo->no_snoop_bits =
231 	fifo->priv_size = sizeof(xge_hal_fifo_txdl_priv_t) +
233 	fifo->priv_size = ((fifo->priv_size + __xge_os_cacheline_size -1) /
238 	fifo->txdl_size = fifo->config->max_frags * sizeof(xge_hal_fifo_txd_t);
239 	txdl_size = ((fifo->txdl_size + __xge_os_cacheline_size - 1) /
242 	if (fifo->txdl_size != txdl_size)
244 	    fifo->config->max_frags, fifo->txdl_size, txdl_size,
247 	fifo->txdl_size = txdl_size;
252 	fifo->channel.dtr_init = attr->dtr_init;
253 	fifo->channel.userdata = attr->userdata;
254 	fifo->txdl_per_memblock = fifo->config->memblock_size /
255 	    fifo->txdl_size;
257 	fifo->mempool = __hal_mempool_create(hldev->pdev,
258 	                     fifo->config->memblock_size,
259 	                     fifo->txdl_size,
260 	                     fifo->priv_size,
265 	                     fifo);
266 	if (fifo->mempool == NULL) {
271 	                (void **) __hal_mempool_items_arr(fifo->mempool),
273 	                fifo->config->reserve_threshold);
282 	    fifo->channel.reserve_length, fifo->channel.reserve_top,
283 	    fifo->config->max_frags, fifo->config->reserve_threshold,
284 	    fifo->config->memblock_size, fifo->config->alignment_size,
285 	    fifo->config->max_aligned_frags);
288 	for ( i = 0; i < fifo->channel.reserve_length; i++) {
290 	    " handle:%p", i, fifo->channel.reserve_arr[i]);
294 	xge_assert(fifo->channel.reserve_length);
296 	max_arr_index   = fifo->channel.reserve_length - 1;
297 	max_arr_index   -=fifo->channel.reserve_top;
299 	mid_point = (fifo->channel.reserve_length - fifo->channel.reserve_top)/2;
301 	    dtrh =  fifo->channel.reserve_arr[i];
302 	    fifo->channel.reserve_arr[i] =
303 	        fifo->channel.reserve_arr[max_arr_index - i];
304 	    fifo->channel.reserve_arr[max_arr_index  - i] = dtrh;
308 	for ( i = 0; i < fifo->channel.reserve_length; i++) {
310 	    " handle:%p", i, fifo->channel.reserve_arr[i]);
320 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
321 	xge_hal_device_t *hldev = (xge_hal_device_t *)fifo->channel.devh;
323 	if (fifo->mempool) {
324 	    __hal_mempool_destroy(fifo->mempool);
330 	xge_os_spin_lock_destroy(&fifo->channel.reserve_lock, hldev->pdev);
332 	xge_os_spin_lock_destroy_irq(&fifo->channel.reserve_lock, hldev->pdev);
336 	    xge_os_spin_lock_destroy(&fifo->channel.post_lock, hldev->pdev);
338 	    xge_os_spin_lock_destroy_irq(&fifo->channel.post_lock,
403 	    if (hldev->config.fifo.queue[i].configured) {
404 	        int priority = hldev->config.fifo.queue[i].priority;
406 	            vBIT((hldev->config.fifo.queue[i].max-1),
423 	                "fifo partition_%d at: "
439 	xge_debug_fifo(XGE_TRACE, "fifo partition_0 at: "
465 	    if (!hldev->config.fifo.queue[i].configured ||
466 	        !hldev->config.fifo.queue[i].intr_vector ||
484 	            hldev->config.fifo.queue[i].intr_vector);
488 	xge_debug_fifo(XGE_TRACE, "%s", "fifo channels initialized");
497 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
502 	    xge_os_dma_unmap(fifo->channel.pdev,
505 	           fifo->align_size,
512 	        xge_os_dma_free(fifo->channel.pdev,
514 	              fifo->align_size,
528 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
535 	txdl_priv->align_vaddr = (char *)xge_os_dma_malloc(fifo->channel.pdev,
536 	            fifo->align_size,
546 	txdl_priv->align_dma_addr = xge_os_dma_map(fifo->channel.pdev,
548 	    fifo->align_size,