nxge/xgehal/xgehal-fifo-fp.c

36 	xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t*)dtrh;
39 	xge_assert(txdp);
41 	            (ulong_t)txdp->host_control;
58 	xge_hal_fifo_txd_t        *txdp    = (xge_hal_fifo_txd_t *)dtrh;
62 	txdp->control_1 |= XGE_HAL_TXD_LIST_OWN_XENA;
66 	    XGE_HAL_SET_TXD_T_CODE(txdp->control_1, XGE_HAL_TXD_T_CODE_UNUSED_5);
91 	if (txdp->control_1 & XGE_HAL_TXD_LSO_COF_CTRL(XGE_HAL_TXD_TCP_LSO)) {
123 	    txdp->control_1, txdp->control_2, txdp->buffer_pointer,
124 	    txdp->host_control, txdl_priv->dma_addr);
135 	          xge_hal_fifo_txd_t *txdp, int list_size, int frags)
143 	        txdp, frags, list_size);
146 	while(txdp){
149 	        txdp, frags, list_size);
150 	    current_txdl_priv = __hal_fifo_txdl_priv(txdp);
154 	    __hal_channel_dtr_free(channelh, txdp);
160 	        txdp = next_txdl_priv->first_txdp;
174 	          xge_hal_fifo_txd_t *txdp, int txdl_count)
183 	current_txdl_priv = __hal_fifo_txdl_priv(txdp);
190 	    txdp = current_txdl_priv->first_txdp;
192 	    __hal_channel_dtr_restore(channelh, (xge_hal_dtr_h )txdp, --i);
194 	        "dtrh %p restored at offset %d", txdp, i);
214 	xge_hal_fifo_txd_t *txdp    = (xge_hal_fifo_txd_t *)dtrh;
216 	return ((char *)(ulong_t)txdp->host_control) +
356 	    xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)*dtrh;
358 	    txdl_priv = __hal_fifo_txdl_priv(txdp);
367 	    txdp->control_1 = txdp->control_2 = 0;
431 	    xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)*dtrh;
434 	    txdl_priv = __hal_fifo_txdl_priv(txdp);
449 	    txdp->control_1 = txdp->control_2 = 0;
655 	xge_hal_fifo_txd_t        *txdp;
662 	txdp = (xge_hal_fifo_txd_t *)*dtrh;
663 	if (txdp == NULL) {
668 	txdl_priv = __hal_fifo_txdl_priv(txdp);
682 	if ( !(txdp->control_1 & XGE_HAL_TXD_LIST_OWN_XENA) ) {
684 	    xge_assert(txdp->host_control!=0);
688 	    *t_code = (u8)XGE_HAL_GET_TXD_T_CODE(txdp->control_1);
844 	xge_hal_fifo_txd_t *txdp;
849 	txdp = (xge_hal_fifo_txd_t *)dtrh + txdl_priv->frags;
852 	    txdp->control_1 = txdp->control_2 = 0;
875 	txdp->buffer_pointer = (u64)txdl_priv->align_dma_addr + prev_boff;
876 	txdp->control_1 |= XGE_HAL_TXD_BUFFER0_SIZE(misaligned_size);
888 	          txdp->buffer_pointer,
896 	    txdp++;
897 	    txdp->buffer_pointer = (u64)dma_pointer +
899 	    txdp->control_1 =
902 	    txdp->control_2 = 0;
976 	xge_hal_fifo_txd_t *txdp;
982 	txdp = (xge_hal_fifo_txd_t *)dtrh + txdl_priv->frags;
985 	    txdp->control_1 = txdp->control_2 = 0;
989 	txdp->buffer_pointer = (u64)txdl_priv->align_dma_addr + prev_boff;
990 	txdp->control_1 |=
1002 	          txdp->buffer_pointer,
1047 	xge_hal_fifo_txd_t *txdp;
1050 	txdp = (xge_hal_fifo_txd_t *)dtrh + txdl_priv->frags;
1053 	    txdp->control_1 = txdp->control_2 = 0;
1063 	txdp->buffer_pointer = (u64)dma_pointer;
1064 	txdp->control_1 |= XGE_HAL_TXD_BUFFER0_SIZE(size);
1090 	xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh;
1092 	txdp->control_1 |= XGE_HAL_TXD_LSO_COF_CTRL(XGE_HAL_TXD_TCP_LSO);
1093 	txdp->control_1 |= XGE_HAL_TXD_TCP_LSO_MSS(mss);
1119 	xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh;
1121 	txdp->control_2 |= cksum_bits;
1137 	xge_hal_fifo_txd_t *txdp = (xge_hal_fifo_txd_t *)dtrh;
1139 	txdp->control_2 |= XGE_HAL_TXD_VLAN_ENABLE;
1140 	txdp->control_2 |= XGE_HAL_TXD_VLAN_TAG(vlan_tag);
1150 	xge_hal_fifo_txd_t *txdp;
1154 	txdp = (xge_hal_fifo_txd_t *)dtrh;
1155 	if (txdp == NULL) {
1160 	if ( !(txdp->control_1 & XGE_HAL_TXD_LIST_OWN_XENA) ) {
1161 	    xge_assert(txdp->host_control!=0);