dev/nxge/if_nxge.c

2723  * @dtr Current Descriptor
2730 xge_rx_compl(xge_hal_channel_h channelh, xge_hal_dtr_h dtr, u8 t_code,
2763 	        xge_hal_device_handle_tcode(channelh, dtr, t_code);
2764 	        xge_hal_ring_dtr_post(channelh,dtr);
2770 	        dtr);
2785 	    xge_ring_dtr_get(mbuf_up, channelh, dtr, lldev, rxd_priv);
2789 	        xge_get_buf(dtr, rxd_priv, lldev, 0) :
2790 	        xge_get_buf_3b_5b(dtr, rxd_priv, lldev);
2801 	        xge_hal_ring_dtr_post(channelh, dtr);
2806 	    xge_hal_ring_dtr_info_get(channelh, dtr, &ext_info);
2813 	    xge_hal_ring_dtr_post(channelh, dtr);
2857 	} while(xge_hal_ring_dtr_next_completed(channelh, &dtr, &t_code)
2873  * @dtr Descriptor
2880 xge_ring_dtr_get(mbuf_t mbuf_up, xge_hal_channel_h channelh, xge_hal_dtr_h dtr,
2899 	        xge_hal_ring_dtr_5b_get(channelh, dtr, dma_data, pkt_length);
2902 	        xge_hal_ring_dtr_3b_get(channelh, dtr, dma_data, pkt_length);
2938 	    xge_hal_ring_dtr_1b_get(channelh, dtr,&dma_data[0], &pkt_length[0]);
3006 	xge_hal_dtr_h            dtr;
3049 	    status = xge_hal_fifo_dtr_reserve(channelh, &dtr);
3058 	    xge_hal_fifo_dtr_vlan_set(dtr, vlan_tag);
3061 	    ll_tx_priv         = xge_hal_fifo_dtr_private(dtr);
3083 	        xge_hal_fifo_dtr_buffer_set(channelh, dtr, count,
3096 	        xge_hal_fifo_dtr_mss_set(dtr, m_head->m_pkthdr.tso_segsz);
3101 	        xge_hal_fifo_dtr_cksum_set_bits(dtr, XGE_HAL_TXD_TX_CKO_IPV4_EN
3106 	    xge_hal_fifo_dtr_post(channelh, dtr);
3264  * @dtr Descriptor
3272 	xge_hal_dtr_h dtr, u8 t_code, void *userdata)
3294 	        xge_hal_device_handle_tcode(channelh, dtr, t_code);
3297 	    ll_tx_priv = xge_hal_fifo_dtr_private(dtr);
3302 	    xge_hal_fifo_dtr_free(channelh, dtr);
3303 	} while(xge_hal_fifo_dtr_next_completed(channelh, &dtr, &t_code)
3505 xge_tx_term(xge_hal_channel_h channelh, xge_hal_dtr_h dtr,
3509 	xge_tx_priv_t *ll_tx_priv = xge_hal_fifo_dtr_private(dtr);