Lines Matching refs:chip
50 #define NANDSIM_CHIP_LOCK(chip) mtx_lock(&(chip)->ns_lock)
51 #define NANDSIM_CHIP_UNLOCK(chip) mtx_unlock(&(chip)->ns_lock)
86 struct nandsim_chip *chip;
92 chip = malloc(sizeof(*chip), M_NANDSIM, M_WAITOK | M_ZERO);
93 if (!chip)
96 mtx_init(&chip->ns_lock, "nandsim lock", NULL, MTX_DEF);
97 callout_init(&chip->ns_callout, 1);
98 STAILQ_INIT(&chip->nandsim_events);
100 chip->chip_num = chip_num;
101 chip->ctrl_num = sim_chip->ctrl_num;
102 chip->sc = sc;
105 nandchip_set_status(chip, NAND_STATUS_WP);
107 chip_param = &chip->params;
109 chip->id.dev_id = sim_chip->device_id;
110 chip->id.man_id = sim_chip->manufact_id;
112 chip->error_ratio = sim_chip->error_ratio;
113 chip->wear_level = sim_chip->wear_level;
114 chip->prog_delay = sim_chip->prog_time;
115 chip->erase_delay = sim_chip->erase_time;
116 chip->read_delay = sim_chip->read_time;
135 init_chip_geom(&chip->cg, chip_param->luns, chip_param->blocks_per_lun,
147 error = nandsim_blk_state_init(chip, size, sim_chip->wear_level);
149 mtx_destroy(&chip->ns_lock);
150 free(chip, M_NANDSIM);
154 error = nandsim_bbm_init(chip, size, sim_chip->bad_block_map);
156 mtx_destroy(&chip->ns_lock);
157 nandsim_blk_state_destroy(chip);
158 free(chip, M_NANDSIM);
162 nandsim_start_handler(chip, poweron_evh);
164 nand_debug(NDBG_SIM,"Create thread for chip%d [%8p]", chip->chip_num,
165 chip);
166 /* Create chip thread */
167 error = kproc_kthread_add(nandsim_loop, chip, &nandsim_proc,
168 &chip->nandsim_td, RFSTOPPED | RFHIGHPID,
169 0, "nandsim", "chip");
171 mtx_destroy(&chip->ns_lock);
172 nandsim_blk_state_destroy(chip);
173 free(chip, M_NANDSIM);
177 thread_lock(chip->nandsim_td);
178 sched_class(chip->nandsim_td, PRI_REALTIME);
179 sched_add(chip->nandsim_td, SRQ_BORING);
180 thread_unlock(chip->nandsim_td);
186 sprintf(swapfile, "chip%d%d.swp", chip->ctrl_num, chip->chip_num);
187 chip->swap = nandsim_swap_init(swapfile, chip_param->blocks_per_lun *
189 if (!chip->swap)
190 nandsim_chip_destroy(chip);
193 tsleep(chip->nandsim_td, PWAIT, "ns_chip", 1 * hz);
195 return (chip);
199 nandsim_blk_state_init(struct nandsim_chip *chip, uint32_t size,
204 if (!chip || size == 0)
207 chip->blk_state = malloc(size * sizeof(struct nandsim_block_state),
209 if (!chip->blk_state) {
215 chip->blk_state[i].wear_lev = wear_lev;
217 chip->blk_state[i].wear_lev = -1;
224 nandsim_blk_state_destroy(struct nandsim_chip *chip)
227 if (chip && chip->blk_state)
228 free(chip->blk_state, M_NANDSIM);
232 nandsim_bbm_init(struct nandsim_chip *chip, uint32_t size,
238 if ((chip == NULL) || (size == 0))
241 if (chip->blk_state == NULL)
255 chip->blk_state[index].is_bad = 1;
262 nandsim_chip_destroy(struct nandsim_chip *chip)
266 ev = create_event(chip, NANDSIM_EV_EXIT, 0);
272 nandsim_chip_freeze(struct nandsim_chip *chip)
275 chip->flags |= NANDSIM_CHIP_FROZEN;
281 struct nandsim_chip *chip = (struct nandsim_chip *)arg;
284 nand_debug(NDBG_SIM,"Start main loop for chip%d [%8p]", chip->chip_num,
285 chip);
287 NANDSIM_CHIP_LOCK(chip);
288 if (!(chip->flags & NANDSIM_CHIP_ACTIVE)) {
289 chip->flags |= NANDSIM_CHIP_ACTIVE;
290 wakeup(chip->nandsim_td);
293 if (STAILQ_EMPTY(&chip->nandsim_events)) {
295 chip->chip_num, chip);
296 msleep(chip, &chip->ns_lock, PRIBIO, "nandev", 0);
299 ev = STAILQ_FIRST(&chip->nandsim_events);
300 STAILQ_REMOVE_HEAD(&chip->nandsim_events, links);
301 NANDSIM_CHIP_UNLOCK(chip);
303 NANDSIM_CHIP_LOCK(chip);
306 while (!STAILQ_EMPTY(&chip->nandsim_events)) {
307 ev = STAILQ_FIRST(&chip->nandsim_events);
308 STAILQ_REMOVE_HEAD(&chip->nandsim_events,
313 NANDSIM_CHIP_UNLOCK(chip);
314 nandsim_log(chip, NANDSIM_LOG_SM, "destroyed\n");
315 mtx_destroy(&chip->ns_lock);
316 nandsim_blk_state_destroy(chip);
317 nandsim_swap_destroy(chip->swap);
318 free(chip, M_NANDSIM);
324 if (!(chip->flags & NANDSIM_CHIP_FROZEN)) {
326 chip->chip_num, ev->type);
327 chip->ev_handler(chip, ev->type, ev->data);
337 create_event(struct nandsim_chip *chip, uint8_t type, uint8_t data_size)
350 ev->chip = chip;
367 struct nandsim_chip *chip = ev->chip;
369 if (!(chip->flags & NANDSIM_CHIP_FROZEN)) {
371 chip->chip_num, chip, ev->type);
373 NANDSIM_CHIP_LOCK(chip);
374 STAILQ_INSERT_TAIL(&chip->nandsim_events, ev, links);
375 NANDSIM_CHIP_UNLOCK(chip);
377 wakeup(chip);
378 if ((ev->type != NANDSIM_EV_TIMEOUT) && chip->nandsim_td &&
379 (curthread != chip->nandsim_td))
395 nandsim_delay(struct nandsim_chip *chip, int timeout)
401 nand_debug(NDBG_SIM,"Chip[%d] Set delay: %d", chip->chip_num, timeout);
403 ev = create_event(chip, NANDSIM_EV_TIMEOUT, 0);
407 chip->sm_state = NANDSIM_STATE_TIMEOUT;
409 if (callout_reset(&chip->ns_callout, tm, nandsim_callout_eh, ev))
412 delay.tv_sec = chip->read_delay / 1000000;
413 delay.tv_usec = chip->read_delay % 1000000;
414 timevaladd(&chip->delay_tv, &delay);
420 nandsim_start_handler(struct nandsim_chip *chip, nandsim_evh_t evh)
424 chip->ev_handler = evh;
426 nand_debug(NDBG_SIM,"Start handler %p for chip%d [%p]", evh,
427 chip->chip_num, chip);
428 ev = create_event(chip, NANDSIM_EV_START, 0);
430 nandsim_sm_error(chip);
436 nandchip_set_data(struct nandsim_chip *chip, uint8_t *data, uint32_t len,
440 nand_debug(NDBG_SIM,"Chip [%x] data %p [%x] at %x", chip->chip_num,
442 chip->data.data_ptr = data;
443 chip->data.size = len;
444 chip->data.index = idx;
448 nandchip_chip_space(struct nandsim_chip *chip, int32_t row, int32_t column,
455 block_size = chip->cg.block_size +
456 (chip->cg.oob_size * chip->cg.pgs_per_blk);
458 err = nand_row_to_blkpg(&chip->cg, row, &lun, &block, &page);
464 if (!nandchip_is_block_valid(chip, block)) {
465 nandchip_set_data(chip, NULL, 0, 0);
469 blk_space = get_bs(chip->swap, block, writing);
471 nandchip_set_data(chip, NULL, 0, 0);
482 offset = page * (chip->cg.page_size + chip->cg.oob_size);
484 nandchip_set_data(chip, &blk_space->blk_ptr[offset], size, column);
490 nandchip_get_addr_byte(struct nandsim_chip *chip, void *data, uint32_t *value)
499 KASSERT((chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW ||
500 chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL),
503 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
504 ncycles = chip->params.address_cycles & 0xf;
505 buffer[chip->sm_addr_cycle++] = byte;
506 } else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
507 ncycles = (chip->params.address_cycles >> 4) & 0xf;
508 buffer[chip->sm_addr_cycle++] = byte;
512 chip->chip_num, byte, chip->sm_addr_cycle, ncycles);
514 if (chip->sm_addr_cycle == ncycles) {
515 chip->sm_addr_cycle = 0;
523 nandchip_is_block_valid(struct nandsim_chip *chip, int block_num)
526 if (!chip || !chip->blk_state)
529 if (chip->blk_state[block_num].wear_lev == 0 ||
530 chip->blk_state[block_num].is_bad)
537 nandchip_set_status(struct nandsim_chip *chip, uint8_t flags)
540 chip->chip_status |= flags;
544 nandchip_clear_status(struct nandsim_chip *chip, uint8_t flags)
547 chip->chip_status &= ~flags;
551 nandchip_get_status(struct nandsim_chip *chip)
553 return (chip->chip_status);
557 nandsim_chip_timeout(struct nandsim_chip *chip)
563 if (chip->sm_state == NANDSIM_STATE_TIMEOUT &&
564 timevalcmp(&tv, &chip->delay_tv, >=)) {
565 nandchip_set_status(chip, NAND_STATUS_RDY);
569 poweron_evh(struct nandsim_chip *chip, uint32_t type, void *data)
574 chip->sm_state = NANDSIM_STATE_IDLE;
579 nandsim_log(chip, NANDSIM_LOG_SM, "in RESET state\n");
580 nandsim_start_handler(chip, reset_evh);
583 nandsim_undefined(chip, type);
587 nandsim_undefined(chip, type);
591 idle_evh(struct nandsim_chip *chip, uint32_t type, void *data)
596 nandsim_log(chip, NANDSIM_LOG_SM, "in IDLE state\n");
597 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
599 nandchip_clear_status(chip, NAND_STATUS_FAIL);
600 getmicrotime(&chip->delay_tv);
604 nandsim_start_handler(chip, readid_evh);
607 nandsim_start_handler(chip, readparam_evh);
610 nandsim_start_handler(chip, read_evh);
613 nandsim_start_handler(chip, write_evh);
616 nandsim_start_handler(chip, erase_evh);
619 nandsim_undefined(chip, type);
623 nandsim_undefined(chip, type);
627 readid_evh(struct nandsim_chip *chip, uint32_t type, void *data)
632 params = &chip->params;
635 nandsim_log(chip, NANDSIM_LOG_SM, "in READID state\n");
636 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_BYTE;
642 nandchip_set_data(chip, (uint8_t *)&chip->id, 2, 0);
644 nandchip_set_data(chip, (uint8_t *)¶ms->signature,
647 nandsim_bad_address(chip, &addr);
649 nandsim_start_handler(chip, idle_evh);
651 nandsim_undefined(chip, type);
655 readparam_evh(struct nandsim_chip *chip, uint32_t type, void *data)
660 params = &chip->params;
663 nandsim_log(chip, NANDSIM_LOG_SM, "in READPARAM state\n");
664 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_BYTE;
669 nandchip_set_data(chip, (uint8_t *)params,
672 nandsim_bad_address(chip, &addr);
674 nandsim_start_handler(chip, idle_evh);
676 nandsim_undefined(chip, type);
680 read_evh(struct nandsim_chip *chip, uint32_t type, void *data)
686 size = chip->cg.page_size + chip->cg.oob_size;
690 nandsim_log(chip, NANDSIM_LOG_SM, "in READ state\n");
691 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_COL;
694 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
695 if (nandchip_get_addr_byte(chip, data, &column))
698 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
699 } else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
700 if (nandchip_get_addr_byte(chip, data, &row))
703 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
705 nandsim_ignore_address(chip, *((uint8_t *)data));
709 if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
711 if (chip->read_delay != 0 &&
712 nandsim_delay(chip, chip->read_delay) == 0)
713 nandchip_clear_status(chip, NAND_STATUS_RDY);
715 nandchip_chip_space(chip, row, column, size, 0);
716 nandchip_set_status(chip, NAND_STATUS_RDY);
717 nandsim_start_handler(chip, idle_evh);
720 nandsim_undefined(chip, type);
723 if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
724 nandchip_chip_space(chip, row, column, size, 0);
725 nandchip_set_status(chip, NAND_STATUS_RDY);
726 nandsim_start_handler(chip, idle_evh);
728 nandsim_undefined(chip, type);
733 write_evh(struct nandsim_chip *chip, uint32_t type, void *data)
740 size = chip->cg.page_size + chip->cg.oob_size;
744 nandsim_log(chip, NANDSIM_LOG_SM, "in WRITE state\n");
745 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_COL;
748 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_COL) {
749 if (nandchip_get_addr_byte(chip, data, &column))
752 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
753 } else if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
754 if (nandchip_get_addr_byte(chip, data, &row))
757 err = nandchip_chip_space(chip, row, column, size, 1);
759 nandchip_set_status(chip, NAND_STATUS_FAIL);
761 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
763 nandsim_ignore_address(chip, *((uint8_t *)data));
767 if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
769 if (chip->prog_delay != 0 &&
770 nandsim_delay(chip, chip->prog_delay) == 0)
771 nandchip_clear_status(chip, NAND_STATUS_RDY);
773 nandchip_set_status(chip, NAND_STATUS_RDY);
774 nandsim_start_handler(chip, idle_evh);
777 nandsim_undefined(chip, type);
780 if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
781 nandsim_start_handler(chip, idle_evh);
782 nandchip_set_status(chip, NAND_STATUS_RDY);
784 nandsim_undefined(chip, type);
790 erase_evh(struct nandsim_chip *chip, uint32_t type, void *data)
797 block_size = chip->cg.block_size +
798 (chip->cg.oob_size * chip->cg.pgs_per_blk);
802 nandsim_log(chip, NANDSIM_LOG_SM, "in ERASE state\n");
803 chip->sm_state = NANDSIM_STATE_WAIT_ADDR_ROW;
807 if (chip->sm_state == NANDSIM_STATE_WAIT_CMD &&
809 if (chip->data.data_ptr != NULL &&
810 chip->data.size == block_size)
811 memset(chip->data.data_ptr, 0xff, block_size);
815 err = nand_row_to_blkpg(&chip->cg, row, &lun,
818 if (chip->blk_state[block].wear_lev > 0)
819 chip->blk_state[block].wear_lev--;
822 if (chip->erase_delay != 0 &&
823 nandsim_delay(chip, chip->erase_delay) == 0)
824 nandchip_clear_status(chip, NAND_STATUS_RDY);
826 nandchip_set_status(chip, NAND_STATUS_RDY);
827 nandsim_start_handler(chip, idle_evh);
830 nandsim_undefined(chip, type);
833 if (chip->sm_state == NANDSIM_STATE_WAIT_ADDR_ROW) {
834 if (nandchip_get_addr_byte(chip, data, &row))
837 err = nandchip_chip_space(chip, row, 0, block_size, 1);
839 nandchip_set_status(chip, NAND_STATUS_FAIL);
841 chip->sm_state = NANDSIM_STATE_WAIT_CMD;
843 nandsim_ignore_address(chip, *((uint8_t *)data));
846 if (chip->sm_state == NANDSIM_STATE_TIMEOUT) {
847 nandchip_set_status(chip, NAND_STATUS_RDY);
848 nandsim_start_handler(chip, idle_evh);
850 nandsim_undefined(chip, type);
856 reset_evh(struct nandsim_chip *chip, uint32_t type, void *data)
860 nandsim_log(chip, NANDSIM_LOG_SM, "in RESET state\n");
861 chip->sm_state = NANDSIM_STATE_TIMEOUT;
862 nandchip_set_data(chip, NULL, 0, 0);
864 nandsim_start_handler(chip, idle_evh);
866 nandsim_undefined(chip, type);
870 nandsim_undefined(struct nandsim_chip *chip, uint8_t type)
873 nandsim_log(chip, NANDSIM_LOG_ERR,
875 type, chip->sm_state);
876 nandsim_start_handler(chip, idle_evh);
880 nandsim_bad_address(struct nandsim_chip *chip, uint8_t *addr)
883 nandsim_log(chip, NANDSIM_LOG_ERR,
890 nandsim_ignore_address(struct nandsim_chip *chip, uint8_t byte)
892 nandsim_log(chip, NANDSIM_LOG_SM, "ignored address byte: %d\n", byte);
896 nandsim_sm_error(struct nandsim_chip *chip)
899 nandsim_log(chip, NANDSIM_LOG_ERR, "ERR: State machine error."