dev/mvs/mvs_pci.c

100 	struct mvs_controller *ctlr = device_get_softc(dev);
106 	ctlr->dev = dev;
112 	ctlr->channels = mvs_ids[i].ports;
113 	ctlr->quirks = mvs_ids[i].quirks;
114 	ctlr->ccc = 0;
116 	    device_get_unit(dev), "ccc", &ctlr->ccc);
117 	ctlr->cccc = 8;
119 	    device_get_unit(dev), "cccc", &ctlr->cccc);
120 	if (ctlr->ccc == 0 || ctlr->cccc == 0) {
121 		ctlr->ccc = 0;
122 		ctlr->cccc = 0;
124 	if (ctlr->ccc > 100000)
125 		ctlr->ccc = 100000;
128 	    ((ctlr->quirks & MVS_Q_GENI) ? "I" :
129 	     ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")),
130 	    ctlr->channels,
131 	    ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"),
132 	    ((ctlr->quirks & MVS_Q_GENI) ?
134 	    ((ctlr->quirks & MVS_Q_GENIIE) ?
136 	mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF);
138 	ctlr->r_rid = PCIR_BAR(0);
139 	if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
140 	    &ctlr->r_rid, RF_ACTIVE)))
143 	ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
144 	ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
145 	ctlr->sc_iomem.rm_type = RMAN_ARRAY;
146 	ctlr->sc_iomem.rm_descr = "I/O memory addresses";
147 	if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
148 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
151 	if ((error = rman_manage_region(&ctlr->sc_iomem,
152 	    rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
153 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
154 		rman_fini(&ctlr->sc_iomem);
161 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
162 		rman_fini(&ctlr->sc_iomem);
166 	for (unit = 0; unit < ctlr->channels; unit++) {
180 	struct mvs_controller *ctlr = device_get_softc(dev);
186 	if (ctlr->irq.r_irq) {
187 		bus_teardown_intr(dev, ctlr->irq.r_irq,
188 		    ctlr->irq.handle);
190 		    ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
194 	rman_fini(&ctlr->sc_iomem);
195 	if (ctlr->r_mem)
196 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
197 	mtx_destroy(&ctlr->mtx);
204 	struct mvs_controller *ctlr = device_get_softc(dev);
205 	int i, ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0;
208 	ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
210 	ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
212 	ATA_OUTL(ctlr->r_mem, CHIP_PCIIC, 0x00000000);
216 		    ctlr->ccc, ctlr->cccc);
220 	if (ctlr->channels > 4 && (ctlr->quirks & MVS_Q_GENI) == 0) {
221 		ATA_OUTL(ctlr->r_mem, CHIP_ICT, cccc);
222 		ATA_OUTL(ctlr->r_mem, CHIP_ITT, ccc);
223 		ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
229 	for (i = 0; i < ctlr->channels / 4; i++) {
231 		ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ICT, cccc);
232 		ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ITT, ccc);
236 		ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_IC, 0x00000000);
239 	ctlr->gmim = (ccim ? ccim : (IC_DONE_HC0 | IC_DONE_HC1)) |
241 	ctlr->mim = ctlr->gmim | ctlr->pmim;
242 	ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
244 	ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x007fffff);
251 	struct mvs_controller *ctlr = device_get_softc(dev);
255 	if (ctlr->ccc == 0)
258 	mtx_lock(&ctlr->mtx);
260 		ctlr->pmim |= bit;
262 		ctlr->pmim &= ~bit;
263 	ctlr->mim = ctlr->gmim | ctlr->pmim;
264 	if (!ctlr->msia)
265 		ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
266 	mtx_unlock(&ctlr->mtx);
272 	struct mvs_controller *ctlr = device_get_softc(dev);
276 	ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
278 	ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
293 	struct mvs_controller *ctlr = device_get_softc(dev);
306 	ctlr->msi = msi;
308 	ctlr->irq.r_irq_rid = msi ? 1 : 0;
309 	if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
310 	    &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
314 	if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL,
315 	    mvs_intr, ctlr, &ctlr->irq.handle))) {
318 		    ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
319 		ctlr->irq.r_irq = NULL;
331 	struct mvs_controller *ctlr = data;
337 	ic = ATA_INL(ctlr->r_mem, CHIP_MIC);
338 	if (ctlr->msi) {
340 		mtx_lock(&ctlr->mtx);
341 		ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0);
342 		ctlr->msia = 1; /* Deny MIM update during processing. */
343 		mtx_unlock(&ctlr->mtx);
348 		ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
349 	for (p = 0; p < ctlr->channels; p++) {
370 			ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic);
375 		    (function = ctlr->interrupt[p].function)) {
376 			arg.arg = ctlr->interrupt[p].argument;
381 	if (ctlr->msi) {
383 		mtx_lock(&ctlr->mtx);
384 		ctlr->msia = 0;	/* Allow MIM update. */
385 		ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
386 		mtx_unlock(&ctlr->mtx);
395 	struct mvs_controller *ctlr = device_get_softc(dev);
403 		st = rman_get_start(ctlr->r_mem);
404 		res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
409 			bsh = rman_get_bushandle(ctlr->r_mem);
410 			bst = rman_get_bustag(ctlr->r_mem);
418 			res = ctlr->irq.r_irq;
446 	struct mvs_controller *ctlr = device_get_softc(dev);
453 	ctlr->interrupt[unit].function = function;
454 	ctlr->interrupt[unit].argument = argument;
462 	struct mvs_controller *ctlr = device_get_softc(dev);
465 	ctlr->interrupt[unit].function = NULL;
466 	ctlr->interrupt[unit].argument = NULL;