dev/mthca/mthca_qp.c

1479 			    int ind, struct ib_ud_wr *wr,
1488 			  mthca_ah_grh_present(to_mah(wr->ah)), 0, 0, 0,
1491 	err = mthca_read_ah(dev, to_mah(wr->ah), &sqp->ud_header);
1502 	switch (wr->wr.opcode) {
1510 		sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
1519 	sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1525 				   wr->pkey_index, &pkey);
1527 	sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1529 	sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
1530 					       sqp->qkey : wr->remote_qkey);
1572 					   struct ib_atomic_wr *wr)
1574 	if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1575 		aseg->swap_add = cpu_to_be64(wr->swap);
1576 		aseg->compare  = cpu_to_be64(wr->compare_add);
1578 		aseg->swap_add = cpu_to_be64(wr->compare_add);
1585 			     struct ib_ud_wr *wr)
1587 	useg->lkey    = cpu_to_be32(to_mah(wr->ah)->key);
1588 	useg->av_addr =	cpu_to_be64(to_mah(wr->ah)->avdma);
1589 	useg->dqpn    =	cpu_to_be32(wr->remote_qpn);
1590 	useg->qkey    =	cpu_to_be32(wr->remote_qkey);
1595 			     struct ib_ud_wr *wr)
1597 	memcpy(useg->av, to_mah(wr->ah)->av, MTHCA_AV_SIZE);
1598 	useg->dqpn = cpu_to_be32(wr->remote_qpn);
1599 	useg->qkey = cpu_to_be32(wr->remote_qkey);
1602 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1632 	for (nreq = 0; wr; ++nreq, wr = wr->next) {
1639 			*bad_wr = wr;
1650 			((wr->send_flags & IB_SEND_SIGNALED) ?
1652 			((wr->send_flags & IB_SEND_SOLICITED) ?
1655 		if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1656 		    wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1657 			((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
1664 			switch (wr->opcode) {
1667 				set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
1668 					      atomic_wr(wr)->rkey);
1671 				set_atomic_seg(wqe, atomic_wr(wr));
1680 				set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1681 					      rdma_wr(wr)->rkey);
1694 			switch (wr->opcode) {
1697 				set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1698 					      rdma_wr(wr)->rkey);
1711 			set_tavor_ud_seg(wqe, ud_wr(wr));
1717 			err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
1721 				*bad_wr = wr;
1729 		if (wr->num_sge > qp->sq.max_gs) {
1732 			*bad_wr = wr;
1736 		for (i = 0; i < wr->num_sge; ++i) {
1737 			mthca_set_data_seg(wqe, wr->sg_list + i);
1751 		qp->wrid[ind + qp->rq.max] = wr->wr_id;
1753 		if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1756 			*bad_wr = wr;
1763 				    mthca_opcode[wr->opcode]);
1767 				    ((wr->send_flags & IB_SEND_FENCE) ?
1772 			op0   = mthca_opcode[wr->opcode];
1773 			f0    = wr->send_flags & IB_SEND_FENCE ?
1805 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1833 	for (nreq = 0; wr; wr = wr->next) {
1840 			*bad_wr = wr;
1855 		if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1857 			*bad_wr = wr;
1861 		for (i = 0; i < wr->num_sge; ++i) {
1862 			mthca_set_data_seg(wqe, wr->sg_list + i);
1867 		qp->wrid[ind] = wr->wr_id;
1916 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1947 	for (nreq = 0; wr; ++nreq, wr = wr->next) {
1980 			*bad_wr = wr;
1989 			((wr->send_flags & IB_SEND_SIGNALED) ?
1991 			((wr->send_flags & IB_SEND_SOLICITED) ?
1993 			((wr->send_flags & IB_SEND_IP_CSUM) ?
1996 		if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1997 		    wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1998 			((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
2005 			switch (wr->opcode) {
2008 				set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2009 					      atomic_wr(wr)->rkey);
2012 				set_atomic_seg(wqe, atomic_wr(wr));
2021 				set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2022 					      rdma_wr(wr)->rkey);
2035 			switch (wr->opcode) {
2038 				set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2039 					      rdma_wr(wr)->rkey);
2052 			set_arbel_ud_seg(wqe, ud_wr(wr));
2058 			err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
2062 				*bad_wr = wr;
2070 		if (wr->num_sge > qp->sq.max_gs) {
2073 			*bad_wr = wr;
2077 		for (i = 0; i < wr->num_sge; ++i) {
2078 			mthca_set_data_seg(wqe, wr->sg_list + i);
2092 		qp->wrid[ind + qp->rq.max] = wr->wr_id;
2094 		if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2097 			*bad_wr = wr;
2104 				    mthca_opcode[wr->opcode]);
2108 				    ((wr->send_flags & IB_SEND_FENCE) ?
2113 			op0   = mthca_opcode[wr->opcode];
2114 			f0    = wr->send_flags & IB_SEND_FENCE ?
2156 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2174 	for (nreq = 0; wr; ++nreq, wr = wr->next) {
2181 			*bad_wr = wr;
2191 		if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2193 			*bad_wr = wr;
2197 		for (i = 0; i < wr->num_sge; ++i) {
2198 			mthca_set_data_seg(wqe, wr->sg_list + i);
2205 		qp->wrid[ind] = wr->wr_id;