Lines Matching refs:BIT_10
180 #define BIT_10 (1 << 10)
283 #define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */
297 #define PCI_PATCH_DIR_2 BIT_10
362 #define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */
394 #define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */
409 #define PEX_LS_TRAIN_ERROR BIT_10 /* Training Error */
792 #define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */
835 #define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */
870 #define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */
1004 #define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */
1104 #define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */
1226 #define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10
1347 #define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */
1371 #define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */
1379 #define PHY_M_PC_FL_GOOD BIT_10 /* Force Link Good */
1427 #define PHY_M_PS_LINK_UP BIT_10 /* Link Up */
1450 #define PHY_M_IS_LST_CHANGE BIT_10 /* Link Status Changed */
1560 #define PHY_M_IRQ_POLARITY BIT_10 /* IRQ polarity */
1616 #define PHY_M_FIB_FORCE_LNK BIT_10 /* Force Link Good */
1815 #define GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */
1881 #define GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */
1911 #define GMR_FS_MC BIT_10 /* Multicast Packet */
1969 #define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */
2067 #define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */
2098 #define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */