dev/msk/if_msk.c

1614 		sc_if->msk_txq = Q_XA1;
1618 		sc_if->msk_txq = Q_XA2;
2964 		    Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
3480 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3970 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3971 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3972 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3973 	CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3978 			CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),
3988 			CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
4004 	msk_set_prefetch(sc, sc_if->msk_txq,
4108 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
4109 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
4111 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
4113 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
4115 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
4118 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
4119 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
4120 	CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
4189 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4190 	val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4193 			CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4195 			val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4202 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
4214 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4218 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
4222 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);