Lines Matching refs:Q_ADDR
3475 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3480 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3970 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3971 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3972 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3973 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3978 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),
3988 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
3994 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3995 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3996 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
3997 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
4001 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
4015 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);
4189 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4190 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4193 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4195 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4214 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4250 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),