dev/msk/if_msk.c

517 		 * speed/flow-control/duplex updates.
1752 	 * Map control/status registers.
2638 	uint32_t control, csum, prod, si;
2773 	control = 0;
2810 		control |= INS_VLAN;
2815 			control |= CALSUM;
2817 			control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
2819 				control |= UDPTCP;
2852 		tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2855 		tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2877 		tx_le->msk_control = htole32(txsegs[i].ds_len | control |
3100 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m)
3109 		if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) {
3111 			if ((control & CSS_IPV4_CSUM_OK) != 0)
3113 			if ((control & (CSS_TCP | CSS_UDP)) != 0 &&
3114 			    (control & (CSS_TCPUDP_CSUM_OK)) != 0) {
3190 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3222 			/* Don't count flow-control packet as errors. */
3249 			msk_rxcsum(sc_if, control, m);
3266 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3287 			/* Don't count flow-control packet as errors. */
3314 			msk_rxcsum(sc_if, control, m);
3336 	uint32_t control;
3357 		control = le32toh(cur_tx->msk_control);
3360 		if ((control & EOP) == 0)
3595 	uint32_t control, status;
3610 		control = le32toh(sd->msk_control);
3611 		if ((control & HW_OWNER) == 0)
3613 		control &= ~HW_OWNER;
3614 		sd->msk_control = htole32(control);
3616 		len = control & STLE_LEN_MASK;
3617 		port = (control >> 16) & 0x01;
3621 			    "0x%08x\n", control & STLE_OP_MASK);
3625 		switch (control & STLE_OP_MASK) {
3640 				msk_jumbo_rxeof(sc_if, status, control, len);
3642 				msk_rxeof(sc_if, status, control, len);
3669 			    control & STLE_OP_MASK);
3844 	 * Initialize GMAC first such that speed/duplex/flow-control
3912 		/* Flush Rx MAC FIFO on any flow control or error. */