Lines Matching refs:targ

284 		struct mprsas_target *targ;
404 targ = &sassc->targets[id];
405 targ->handle = 0x0;
406 targ->encl_slot = 0x0;
407 targ->encl_handle = 0x0;
408 targ->encl_level_valid = 0x0;
409 targ->encl_level = 0x0;
410 targ->connector_name[0] = ' ';
411 targ->connector_name[1] = ' ';
412 targ->connector_name[2] = ' ';
413 targ->connector_name[3] = ' ';
414 targ->exp_dev_handle = 0x0;
415 targ->phy_num = 0x0;
416 targ->linkrate = 0x0;
417 mprsas_rescan_target(sc, targ);
419 targ->tid);
428 targ = mprsas_find_target_by_handle(sassc, 0,
430 if (targ == NULL)
432 targ->flags |= MPR_TARGET_FLAGS_RAID_COMPONENT;
433 mprsas_rescan_target(sc, targ);
491 struct mprsas_target *targ;
503 targ =
506 if (targ) {
535 struct mprsas_target *targ;
580 targ = mprsas_find_target_by_handle(
583 if (targ) {
584 targ->flags |=
597 targ = mprsas_find_target_by_handle(
600 if (targ) {
601 targ->flags |=
806 struct mprsas_target *targ;
905 targ = &sassc->targets[id];
906 if (!(targ->flags & MPR_TARGET_FLAGS_RAID_COMPONENT)) {
914 if (targ->handle != 0x0) {
916 "target id %d handle 0x%04x\n", id, targ->handle);
924 targ->devinfo = device_info;
925 targ->devname = le32toh(config_page.DeviceName.High);
926 targ->devname = (targ->devname << 32) |
928 targ->encl_handle = le16toh(config_page.EnclosureHandle);
929 targ->encl_slot = le16toh(config_page.Slot);
930 targ->encl_level = config_page.EnclosureLevel;
931 targ->connector_name[0] = config_page.ConnectorName[0];
932 targ->connector_name[1] = config_page.ConnectorName[1];
933 targ->connector_name[2] = config_page.ConnectorName[2];
934 targ->connector_name[3] = config_page.ConnectorName[3];
935 targ->handle = handle;
936 targ->parent_handle = le16toh(config_page.ParentDevHandle);
937 targ->sasaddr = mpr_to_u64(&config_page.SASAddress);
938 targ->parent_sasaddr = le64toh(parent_sas_address);
939 targ->parent_devinfo = parent_devinfo;
940 targ->tid = id;
941 targ->linkrate = (linkrate>>4);
942 targ->flags = 0;
944 targ->flags = MPR_TARGET_IS_SATA_SSD;
950 targ->scsi_req_desc_type =
955 targ->encl_level_valid = TRUE;
957 TAILQ_INIT(&targ->commands);
958 TAILQ_INIT(&targ->timedout_commands);
959 while (!SLIST_EMPTY(&targ->luns)) {
960 lun = SLIST_FIRST(&targ->luns);
961 SLIST_REMOVE_HEAD(&targ->luns, lun_link);
964 SLIST_INIT(&targ->luns);
966 mpr_describe_devinfo(targ->devinfo, devstring, 80);
969 mpr_describe_table(mpr_linkrate_names, targ->linkrate),
970 targ->handle, targ->encl_handle, targ->encl_slot);
971 if (targ->encl_level_valid) {
973 "and connector name (%4s)\n", targ->encl_level,
974 targ->connector_name);
980 mprsas_rescan_target(sc, targ);
981 mpr_dprint(sc, MPR_MAPPING, "Target id 0x%x added\n", targ->tid);
994 targ->timeouts++;
997 if ((targ->tm = mprsas_alloc_tm(sc)) != NULL) {
1001 targ->tm->cm_targ = targ;
1002 mprsas_send_reset(sc, targ->tm,
1267 struct mprsas_target *targ;
1337 targ = &sassc->targets[id];
1338 targ->devinfo = device_info;
1339 targ->encl_handle = le16toh(config_page.EnclosureHandle);
1340 targ->encl_slot = le16toh(config_page.Slot);
1341 targ->encl_level = config_page.EnclosureLevel;
1342 targ->connector_name[0] = ((char *)&config_page.ConnectorName)[0];
1343 targ->connector_name[1] = ((char *)&config_page.ConnectorName)[1];
1344 targ->connector_name[2] = ((char *)&config_page.ConnectorName)[2];
1345 targ->connector_name[3] = ((char *)&config_page.ConnectorName)[3];
1346 targ->is_nvme = device_info & MPI26_PCIE_DEVINFO_NVME;
1347 targ->MDTS = config_page2.MaximumDataTransferSize;
1352 targ->encl_level_valid = TRUE;
1353 targ->handle = handle;
1354 targ->parent_handle = le16toh(config_page.ParentDevHandle);
1355 targ->sasaddr = mpr_to_u64(&config_page.WWID);
1356 targ->parent_sasaddr = le64toh(parent_wwid);
1357 targ->parent_devinfo = parent_devinfo;
1358 targ->tid = id;
1359 targ->linkrate = linkrate;
1360 targ->flags = 0;
1365 targ->scsi_req_desc_type =
1368 TAILQ_INIT(&targ->commands);
1369 TAILQ_INIT(&targ->timedout_commands);
1370 while (!SLIST_EMPTY(&targ->luns)) {
1371 lun = SLIST_FIRST(&targ->luns);
1372 SLIST_REMOVE_HEAD(&targ->luns, lun_link);
1375 SLIST_INIT(&targ->luns);
1377 mpr_describe_devinfo(targ->devinfo, devstring, 80);
1380 mpr_describe_table(mpr_pcie_linkrate_names, targ->linkrate),
1381 targ->handle, targ->encl_handle, targ->encl_slot);
1382 if (targ->encl_level_valid) {
1384 "and connector name (%4s)\n", targ->encl_level,
1385 targ->connector_name);
1391 mprsas_rescan_target(sc, targ);
1392 mpr_dprint(sc, MPR_MAPPING, "Target id 0x%x added\n", targ->tid);
1403 struct mprsas_target *targ;
1429 targ = &sassc->targets[id];
1430 targ->tid = id;
1431 targ->handle = handle;
1432 targ->devname = wwid;
1433 TAILQ_INIT(&targ->commands);
1434 TAILQ_INIT(&targ->timedout_commands);
1435 while (!SLIST_EMPTY(&targ->luns)) {
1436 lun = SLIST_FIRST(&targ->luns);
1437 SLIST_REMOVE_HEAD(&targ->luns, lun_link);
1440 SLIST_INIT(&targ->luns);
1445 mprsas_rescan_target(sc, targ);
1447 targ->tid, wwid);