mlx5/mlx5_fpga/mlx5fpga_xfer.c

35 #include <dev/mlx5/mlx5_fpga/xfer.h>
39 	const struct mlx5_fpga_transaction *xfer;
63 	const struct mlx5_fpga_transaction *xfer = xfer_state->xfer;
67 	xfer->complete1(xfer, status);
79 	ddr_base = mlx5_fpga_ddr_base_get(xfer_state->xfer->conn->fdev);
80 	page_size = (xfer_state->xfer->addr + xfer_state->pos < ddr_base) ?
89 		left = xfer_state->xfer->size - xfer_state->pos;
99 		pos_addr = xfer_state->xfer->addr + xfer_state->pos;
100 		pos_data = xfer_state->xfer->data + xfer_state->pos;
112 		xfer_trans->transaction.conn = xfer_state->xfer->conn;
114 		xfer_trans->transaction.direction = xfer_state->xfer->direction;
119 		mlx5_fpga_dbg(xfer_state->xfer->conn->fdev, "Starting %zu bytes at %p done; %u started %u inflight %u done %u error\n",
134 				mlx5_fpga_warn(xfer_state->xfer->conn->fdev, "Transfer failed to start transaction: %d. %u started %u done %u error\n",
195 int mlx5_fpga_xfer_exec(const struct mlx5_fpga_transaction *xfer)
197 	u64 base = mlx5_fpga_ddr_base_get(xfer->conn->fdev);
198 	u64 size = mlx5_fpga_ddr_size_get(xfer->conn->fdev);
204 	if (xfer->addr + xfer->size > base + size) {
205 		mlx5_fpga_warn(xfer->conn->fdev, "Transfer ends at %jx outside of DDR range %jx\n",
206 			       (uintmax_t)(xfer->addr + xfer->size), (uintmax_t)(base + size));
210 	if (xfer->addr & MLX5_FPGA_TRANSACTION_SEND_ALIGN_BITS) {
211 		mlx5_fpga_warn(xfer->conn->fdev, "Transfer address %jx not aligned\n",
212 			       (uintmax_t)xfer->addr);
216 	if (xfer->size & MLX5_FPGA_TRANSACTION_SEND_ALIGN_BITS) {
217 		mlx5_fpga_warn(xfer->conn->fdev, "Transfer size %zu not aligned\n",
218 			       xfer->size);
222 	if (xfer->size < 1) {
223 		mlx5_fpga_warn(xfer->conn->fdev, "Empty transfer size %zu not allowed\n",
224 			       xfer->size);
229 	xfer_state->xfer = xfer;