mlx5/mlx5_fpga/mlx5fpga_core.c

66 static void client_context_destroy(struct mlx5_fpga_device *fdev,
69 	mlx5_fpga_dbg(fdev, "Deleting client context %p of client %p\n",
72 		context->client->destroy(fdev);
77 static int client_context_create(struct mlx5_fpga_device *fdev,
90 	list_add(&context->list, &fdev->client_data_list);
92 	mlx5_fpga_dbg(fdev, "Adding client context %p client %p\n",
96 		client->create(fdev);
105 	struct mlx5_fpga_device *fdev = NULL;
107 	fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
108 	if (!fdev)
111 	spin_lock_init(&fdev->state_lock);
112 	init_completion(&fdev->load_event);
113 	fdev->fdev_state = MLX5_FDEV_STATE_NONE;
114 	INIT_LIST_HEAD(&fdev->client_data_list);
115 	return fdev;
149 static int mlx5_fpga_device_load_check(struct mlx5_fpga_device *fdev)
155 	err = mlx5_fpga_query(fdev->mdev, &query);
157 		mlx5_fpga_err(fdev, "Failed to query status: %d\n", err);
161 	fdev->last_admin_image = query.admin_image;
162 	fdev->last_oper_image = query.oper_image;
163 	fdev->image_status = query.image_status;
165 	mlx5_fpga_info(fdev, "Status %u; Admin image %u; Oper image %u\n",
169 	fpga_id = MLX5_CAP_FPGA(fdev->mdev, fpga_id);
174 		mlx5_fpga_err(fdev, "%s image failed to load; status %u\n",
175 			      mlx5_fpga_image_name(fdev->last_oper_image),
183 static int mlx5_fpga_device_brb(struct mlx5_fpga_device *fdev)
186 	struct mlx5_core_dev *mdev = fdev->mdev;
190 		mlx5_fpga_err(fdev, "Failed to set bypass on: %d\n", err);
195 		mlx5_fpga_err(fdev, "Failed to reset SBU: %d\n", err);
200 		mlx5_fpga_err(fdev, "Failed to set bypass off: %d\n", err);
209 	struct mlx5_fpga_device *fdev = mdev->fpga;
219 	if (!fdev)
222 	err = mlx5_fpga_caps(fdev->mdev);
226 	err = mlx5_fpga_device_load_check(fdev);
230 	fpga_id = MLX5_CAP_FPGA(fdev->mdev, fpga_id);
231 	mlx5_fpga_info(fdev, "FPGA card %s\n", mlx5_fpga_name(fpga_id));
236 	mlx5_fpga_info(fdev, "%s(%d) image, version %u; SBU %06x:%04x version %d\n",
237 		       mlx5_fpga_image_name(fdev->last_oper_image),
238 		       fdev->last_oper_image,
239 		       MLX5_CAP_FPGA(fdev->mdev, image_version),
240 		       MLX5_CAP_FPGA(fdev->mdev, ieee_vendor_id),
241 		       MLX5_CAP_FPGA(fdev->mdev, sandbox_product_id),
242 		       MLX5_CAP_FPGA(fdev->mdev, sandbox_product_version));
251 	err = mlx5_fpga_conn_device_init(fdev);
258 	err = mlx5_fpga_trans_device_init(fdev);
260 		mlx5_fpga_err(fdev, "Failed to init transaction: %d\n",
268 	conn_attr.cb_arg = fdev;
271 	conn = mlx5_fpga_conn_create(fdev, &conn_attr,
275 		mlx5_fpga_err(fdev, "Failed to create shell conn: %d\n", err);
281 	fdev->shell_conn = conn;
283 	if (fdev->last_oper_image == MLX5_FPGA_IMAGE_USER) {
284 		err = mlx5_fpga_device_brb(fdev);
288 		vid = MLX5_CAP_FPGA(fdev->mdev, ieee_vendor_id);
289 		pid = MLX5_CAP_FPGA(fdev->mdev, sandbox_product_id);
291 		list_for_each_entry(client_context, &fdev->client_data_list,
293 			if (client_context->client->add(fdev, vid, pid))
303 	if (fdev->shell_conn) {
306 		mlx5_fpga_conn_destroy(fdev->shell_conn);
308 		fdev->shell_conn = NULL;
315 	mlx5_fpga_trans_device_cleanup(fdev);
320 	mlx5_fpga_conn_device_cleanup(fdev);
326 	spin_lock_irqsave(&fdev->state_lock, flags);
327 	fdev->fdev_state = err ? MLX5_FDEV_STATE_FAILURE : MLX5_FDEV_STATE_SUCCESS;
328 	spin_unlock_irqrestore(&fdev->state_lock, flags);
334 	struct mlx5_fpga_device *fdev = NULL;
344 	fdev = mlx5_fpga_device_alloc();
345 	if (!fdev)
348 	fdev->mdev = mdev;
349 	mdev->fpga = fdev;
353 	list_add_tail(&fdev->list, &mlx5_fpga_devices);
355 		client_context_create(fdev, client, NULL);
364 	struct mlx5_fpga_device *fdev = mdev->fpga;
370 	if (!fdev)
377 	spin_lock_irqsave(&fdev->state_lock, flags);
379 	if (fdev->fdev_state != MLX5_FDEV_STATE_SUCCESS) {
380 		spin_unlock_irqrestore(&fdev->state_lock, flags);
383 	fdev->fdev_state = MLX5_FDEV_STATE_NONE;
384 	spin_unlock_irqrestore(&fdev->state_lock, flags);
386 	if (fdev->last_oper_image == MLX5_FPGA_IMAGE_USER) {
389 			mlx5_fpga_err(fdev, "Failed to re-set SBU bypass on: %d\n",
394 	list_for_each_entry(client_context, &fdev->client_data_list, list) {
397 		client_context->client->remove(fdev);
402 	if (fdev->shell_conn) {
405 		mlx5_fpga_conn_destroy(fdev->shell_conn);
407 		fdev->shell_conn = NULL;
408 		mlx5_fpga_trans_device_cleanup(fdev);
412 	mlx5_fpga_conn_device_cleanup(fdev);
421 	struct mlx5_fpga_device *fdev = mdev->fpga;
423 	if (!fdev)
430 	list_for_each_entry_safe(context, tmp, &fdev->client_data_list, list)
431 		client_context_destroy(fdev, context);
433 	list_del(&fdev->list);
434 	kfree(fdev);
456 	struct mlx5_fpga_device *fdev = mdev->fpga;
472 		mlx5_fpga_err(fdev, "Error %u on QP %u: %s\n",
476 		mlx5_fpga_warn_ratelimited(fdev, "Unexpected event %u\n",
481 	spin_lock_irqsave(&fdev->state_lock, flags);
482 	switch (fdev->fdev_state) {
484 		mlx5_fpga_warn(fdev, "Error %u: %s\n", syndrome, event_name);
489 			mlx5_fpga_warn(fdev, "Error while loading %u: %s\n",
491 		complete(&fdev->load_event);
494 		mlx5_fpga_warn_ratelimited(fdev, "Unexpected error event %u: %s\n",
497 	spin_unlock_irqrestore(&fdev->state_lock, flags);
504 		mlx5_trigger_health_work(fdev->mdev);
510 	struct mlx5_fpga_device *fdev;
523 	list_for_each_entry(fdev, &mlx5_fpga_devices, list) {
524 		err = client_context_create(fdev, client, &context);
528 		spin_lock_irqsave(&fdev->state_lock, flags);
529 		call_add = (fdev->fdev_state == MLX5_FDEV_STATE_SUCCESS);
530 		spin_unlock_irqrestore(&fdev->state_lock, flags);
533 			vid = MLX5_CAP_FPGA(fdev->mdev, ieee_vendor_id);
534 			pid = MLX5_CAP_FPGA(fdev->mdev, sandbox_product_id);
535 			if (!client->add(fdev, vid, pid))
547 	struct mlx5_fpga_device *fdev;
553 	list_for_each_entry(fdev, &mlx5_fpga_devices, list) {
555 					 &fdev->client_data_list,
560 				client->remove(fdev);
561 			client_context_destroy(fdev, context);