Lines Matching refs:ull
58 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
59 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
60 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
61 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
62 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
63 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
64 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
65 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
66 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
67 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
68 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
69 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT) | \
70 (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE))
549 async_event_mask |= (1ull <<
553 async_event_mask |= (1ull <<
557 async_event_mask |= (1ull <<
561 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) |
562 (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR);
565 async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT);
568 async_event_mask |= (1ull <<
573 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,