dev/mlx5/device.h

957 #define MLX5_CAP_GEN(mdev, cap) \
958 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
960 #define MLX5_CAP_GEN_MAX(mdev, cap) \
961 	MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
963 #define MLX5_CAP_ETH(mdev, cap) \
965 		 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
967 #define MLX5_CAP_ETH_MAX(mdev, cap) \
969 		 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
971 #define MLX5_CAP_ROCE(mdev, cap) \
972 	MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
974 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
975 	MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
977 #define MLX5_CAP_ATOMIC(mdev, cap) \
978 	MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
980 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
981 	MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
983 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
984 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
986 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
987 	MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
989 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
991 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
993 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
995 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
997 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
998 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1000 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1001 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1003 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1004 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1006 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1007 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1009 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1010 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1012 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1013 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1015 #define MLX5_CAP_ESW(mdev, cap) \
1017 		 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1019 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1021 		 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1023 #define MLX5_CAP_ODP(mdev, cap)\
1024 	MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1026 #define MLX5_CAP_ODP_MAX(mdev, cap)\
1027 	MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1029 #define MLX5_CAP_SNAPSHOT(mdev, cap) \
1031 		 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1033 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \
1035 		 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1037 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \
1039 		 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1041 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \
1043 		 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1045 #define MLX5_CAP_DEBUG(mdev, cap) \
1047 		 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1049 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \
1051 		 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1053 #define MLX5_CAP_QOS(mdev, cap) \
1055 		 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1057 #define MLX5_CAP_QOS_MAX(mdev, cap) \
1059 		 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1079 #define MLX5_CAP_FPGA(mdev, cap) \
1080 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1082 #define MLX5_CAP64_FPGA(mdev, cap) \
1083 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)