Lines Matching refs:entries
169 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
1610 * Reserved MTT entries must be aligned up to a cacheline
1612 * writes to all other MTT entries. (The variable
2838 struct msix_entry *entries;
2850 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2851 if (!entries)
2855 entries[i].entry = i;
2857 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2861 kfree(entries);
2867 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2876 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2912 kfree(entries);