Lines Matching defs:inbox

180 	u32 *inbox;
191 inbox = mailbox->buf;
193 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
194 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
326 struct mlx4_cmd_mailbox *inbox,
1255 struct mlx4_cmd_mailbox *inbox,
1389 struct mlx4_cmd_mailbox *inbox,
1724 struct mlx4_cmd_mailbox *inbox,
1817 __be32 *inbox;
1878 inbox = mailbox->buf;
1886 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1888 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1893 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1897 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1901 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1905 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1909 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13);
1913 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1922 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1937 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1947 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31);
1951 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1952 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1953 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1954 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1955 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1956 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1957 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1958 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1959 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1960 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1961 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
1962 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1963 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1968 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1972 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1973 MLX4_PUT(inbox, param->log_mc_entry_sz,
1975 MLX4_PUT(inbox, param->log_mc_table_sz,
1982 MLX4_PUT(inbox,
1985 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1990 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1992 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1997 MLX4_PUT(inbox,
2002 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
2003 MLX4_PUT(inbox, param->log_mc_entry_sz,
2005 MLX4_PUT(inbox, param->log_mc_hash_sz,
2007 MLX4_PUT(inbox, param->log_mc_table_sz,
2010 MLX4_PUT(inbox, (u8) (1 << 3),
2016 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
2017 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
2018 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
2019 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
2020 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
2024 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
2025 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
2030 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
2213 struct mlx4_cmd_mailbox *inbox,
2257 u32 *inbox;
2280 inbox = mailbox->buf;
2285 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
2288 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
2290 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
2292 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
2311 struct mlx4_cmd_mailbox *inbox,
2877 struct mlx4_cmd_mailbox *inbox, *outbox;
2881 inbox = mlx4_alloc_cmd_mailbox(dev);
2882 if (IS_ERR(inbox))
2883 return PTR_ERR(inbox);
2887 mlx4_free_cmd_mailbox(dev, inbox);
2891 inbuf = inbox->buf;
2905 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2921 mlx4_free_cmd_mailbox(dev, inbox);
2953 struct mlx4_cmd_mailbox *inbox,
2957 struct mlx4_access_reg *inbuf = inbox->buf;
2974 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,