Lines Matching refs:reg_val
458 uint32_t reg_idx, reg_off, reg_val, i;
463 reg_val = (1 | (queue << 1)) << reg_off;
467 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val);
477 uint32_t reg_val, i;
485 reg_val = ((1 | (queue << 1)) | (1 | (queue << 1)) << 8 |
489 MGE_WRITE(sc, MGE_DA_FILTER_SPEC_MCAST(i), reg_val);
490 MGE_WRITE(sc, MGE_DA_FILTER_OTH_MCAST(i), reg_val);
494 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val);
1091 volatile uint32_t reg_val;
1146 reg_val = mge_set_port_serial_control(media_status);
1147 MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
1180 reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
1181 reg_val |= PORT_SERIAL_ENABLE;
1182 MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
1185 reg_val = MGE_READ(sc, MGE_PORT_STATUS);
1186 if (reg_val & MGE_STATUS_LINKUP)
1762 uint32_t reg_val, queued = 0;
1811 reg_val = MGE_READ(sc, MGE_TX_QUEUE_CMD);
1812 MGE_WRITE(sc, MGE_TX_QUEUE_CMD, reg_val | MGE_ENABLE_TXQ);
1821 volatile uint32_t reg_val, status;
1842 reg_val = MGE_READ(sc, MGE_TX_QUEUE_CMD);
1843 MGE_WRITE(sc, MGE_TX_QUEUE_CMD, reg_val | MGE_DISABLE_TXQ);
1876 reg_val = MGE_READ(sc, MGE_PORT_STATUS);
1877 if ( !(reg_val & MGE_STATUS_TX_IN_PROG) &&
1878 (reg_val & MGE_STATUS_TX_FIFO_EMPTY))
1888 reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
1889 reg_val &= ~(PORT_SERIAL_ENABLE);
1890 MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL ,reg_val);