Lines Matching refs:cmd_status
420 mfi_init->header.cmd_status = MFI_STAT_INVALID_STATUS;
431 if (mfi_init->header.cmd_status == MFI_STAT_OK) {
435 mfi_init->header.cmd_status);
436 error = mfi_init->header.cmd_status;
605 mfi_cmd->cm_frame->header.cmd_status = MFI_STAT_OK;
606 mfi_cmd->cm_frame->dcmd.header.cmd_status = MFI_STAT_OK;
612 mfi_cmd->cm_frame->header.cmd_status = status;
614 mfi_cmd->cm_frame->dcmd.header.cmd_status = status;
620 mfi_cmd->cm_frame->header.cmd_status = ext_status;
621 mfi_cmd->cm_frame->dcmd.header.cmd_status = ext_status;
626 mfi_cmd->cm_frame->header.cmd_status = status;
627 mfi_cmd->cm_frame->dcmd.header.cmd_status = status;
631 mfi_cmd->cm_frame->header.cmd_status = status;
632 mfi_cmd->cm_frame->dcmd.header.cmd_status = status;
706 status = cmd_mfi->cm_frame->dcmd.header.cmd_status;
715 cmd_mfi->cm_frame->header.cmd_status = MFI_STAT_OK;
1104 hdr->cmd_status = MFI_STAT_INVALID_STATUS;
1150 * The value of hdr->cmd_status is updated directly by the hardware
1154 while (hdr->cmd_status == MFI_STAT_INVALID_STATUS) {
1171 if (hdr->cmd_status == MFI_STAT_INVALID_STATUS) {
1389 if (hdr->cmd_status != MFI_STAT_OK) {
1391 hdr->cmd_status);
1467 hdr->cmd_status == MFI_STAT_INVALID_STATUS) {