dev/lmc/if_lmc.c

157     WRITE_CSR(TLP_SROM_MII, csr);
159     WRITE_CSR(TLP_SROM_MII, csr);
161     WRITE_CSR(TLP_SROM_MII, csr);
175   WRITE_CSR(TLP_SROM_MII, csr);
178   WRITE_CSR(TLP_SROM_MII, csr);	/* assert CS */
186     WRITE_CSR(TLP_SROM_MII, csr);
188     WRITE_CSR(TLP_SROM_MII, csr);
191   WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOE);
207   WRITE_CSR(TLP_SROM_MII, csr);
211   WRITE_CSR(TLP_SROM_MII, csr);	/* assert CS */
215   WRITE_CSR(TLP_SROM_MII, csr);	/* deassert CS */
219   WRITE_CSR(TLP_SROM_MII, csr);	/* assert CS */
223   WRITE_CSR(TLP_SROM_MII, csr);	/* deassert CS */
227   WRITE_CSR(TLP_SROM_MII, csr);	/* assert CS */
234   WRITE_CSR(TLP_SROM_MII, csr);	/* deassert CS */
238   WRITE_CSR(TLP_SROM_MII, csr);	/* assert CS */
244   WRITE_CSR(TLP_SROM_MII, csr);	/* deassert CS */
247   WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOE);
258   WRITE_CSR(TLP_BIOS_ROM, addr);
262   WRITE_CSR(TLP_SROM_MII, srom_mii);
271   WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOE);
282   WRITE_CSR(TLP_BIOS_ROM, addr);
289   WRITE_CSR(TLP_SROM_MII, srom_mii);
295   WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOE);
379     WRITE_CSR(TLP_SROM_MII, csr);
381     WRITE_CSR(TLP_SROM_MII, csr);
383     WRITE_CSR(TLP_SROM_MII, csr);
396   WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOUT);
406   WRITE_CSR(TLP_SROM_MII, csr);
413     WRITE_CSR(TLP_SROM_MII, csr);
415     WRITE_CSR(TLP_SROM_MII, csr);
423   WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOUT);
432   WRITE_CSR(TLP_SROM_MII, TLP_MII_MDOE);
533   WRITE_CSR(TLP_GPIO, TLP_GPIO_DIR | (sc->gpio_dir));
540   WRITE_CSR(TLP_GPIO, TLP_GPIO_DIR | (sc->gpio_dir));
552   WRITE_CSR(TLP_GPIO, (read_gpio(sc) |  bits) & 0xFF);
558   WRITE_CSR(TLP_GPIO, (read_gpio(sc) & ~bits) & 0xFF);
2734   WRITE_CSR(TLP_RX_POLL, 1);
2942   WRITE_CSR(TLP_TX_POLL, 1);
2990       WRITE_CSR(TLP_OP_MODE, op_mode & ~TLP_OP_TX_RUN);
2993       WRITE_CSR(TLP_OP_MODE, op_mode); /* restart tx */
3012       WRITE_CSR(TLP_OP_MODE, op_mode & ~TLP_OP_RX_RUN);
3015       WRITE_CSR(TLP_OP_MODE, op_mode);  /* restart rx */
3045   WRITE_CSR(TLP_STATUS, READ_CSR(TLP_STATUS));
3124     WRITE_CSR(TLP_INT_ENBL, TLP_INT_DISABLE);
3132   WRITE_CSR(TLP_INT_ENBL, TLP_INT_DISABLE);
3137   WRITE_CSR(TLP_INT_ENBL, TLP_INT_TXRX);
3354     WRITE_CSR(TLP_OP_MODE, op_mode);
3364     WRITE_CSR(TLP_OP_MODE, op_mode);
3452         WRITE_CSR(ioctl->address*TLP_CSR_STRIDE, ioctl->data);
3528   WRITE_CSR(TLP_TIMER, 0xFFFF);
4224   WRITE_CSR(TLP_BUS_MODE, TLP_BUS_RESET); /* self-clearing */
4241   WRITE_CSR(TLP_BUS_MODE,
4270   WRITE_CSR(TLP_TX_LIST, sc->txring.dma_addr);
4272   WRITE_CSR(TLP_RX_LIST, sc->rxring.dma_addr);
4275   WRITE_CSR(TLP_OP_MODE, TLP_OP_INIT | (tlp_op_tr<<TLP_OP_TR_SHIFT));
4281   WRITE_CSR(TLP_WDOG, TLP_WDOG_INIT);
4284   WRITE_CSR(TLP_INT_ENBL, TLP_INT_TXRX);
4299   WRITE_CSR(TLP_BUS_MODE, TLP_BUS_RESET); /* self-clearing */