Lines Matching defs:oct
46 lio_cn23xx_pf_soft_reset(struct octeon_device *oct)
49 lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF);
51 lio_dev_dbg(oct, "BIST enabled for CN23XX soft reset\n");
53 lio_write_csr64(oct, LIO_CN23XX_SLI_SCRATCH1, 0x1234ULL);
56 lio_pci_readq(oct, LIO_CN23XX_RST_SOFT_RST);
57 lio_pci_writeq(oct, 1, LIO_CN23XX_RST_SOFT_RST);
62 if (lio_read_csr64(oct, LIO_CN23XX_SLI_SCRATCH1)) {
63 lio_dev_err(oct, "Soft reset failed\n");
67 lio_dev_dbg(oct, "Reset completed\n");
70 lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF);
76 lio_cn23xx_pf_enable_error_reporting(struct octeon_device *oct)
80 regval = lio_read_pci_cfg(oct, LIO_CN23XX_CFG_PCIE_DEVCTL);
85 lio_read_pci_cfg(oct,
88 lio_read_pci_cfg(oct,
90 lio_dev_err(oct, "PCI-E Fatal error detected;\n"
100 lio_dev_dbg(oct, "Enabling PCI-E error reporting..\n");
101 lio_write_pci_cfg(oct, LIO_CN23XX_CFG_PCIE_DEVCTL, regval);
105 lio_cn23xx_pf_coprocessor_clock(struct octeon_device *oct)
113 return (((lio_pci_readq(oct, LIO_CN23XX_RST_BOOT) >> 24) & 0x3f) * 50);
117 lio_cn23xx_pf_get_oq_ticks(struct octeon_device *oct, uint32_t time_intr_in_us)
120 uint32_t oqticks_per_us = lio_cn23xx_pf_coprocessor_clock(oct);
122 oct->pfvf_hsword.coproc_tics_per_us = oqticks_per_us;
141 lio_cn23xx_pf_setup_global_mac_regs(struct octeon_device *oct)
144 uint16_t mac_no = oct->pcie_port;
145 uint16_t pf_num = oct->pf_num;
148 lio_dev_dbg(oct, "%s: Using pcie port %d\n", __func__, mac_no);
152 lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num));
159 (oct->sriov_info.trs << LIO_CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS);
162 lio_write_csr64(oct, LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num),
165 lio_dev_dbg(oct, "SLI_PKT_MAC(%d)_PF(%d)_RINFO : 0x%016llx\n", mac_no,
167 LIO_CAST64(lio_read_csr64(oct,
173 lio_cn23xx_pf_reset_io_queues(struct octeon_device *oct)
180 srn = oct->sriov_info.pf_srn;
181 ern = srn + oct->sriov_info.num_pf_rings;
189 d64 = lio_read_csr64(oct,
192 lio_write_csr64(oct,
199 lio_read_csr64(oct,
204 reg_val = lio_read_csr64(oct,
210 lio_dev_err(oct,
217 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
220 reg_val = lio_read_csr64(oct,
223 lio_dev_err(oct, "clearing the reset failed for qno: %u\n",
233 lio_cn23xx_pf_setup_global_input_regs(struct octeon_device *oct)
235 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
241 pf_num = oct->pf_num;
243 srn = oct->sriov_info.pf_srn;
244 ern = srn + oct->sriov_info.num_pf_rings;
246 if (lio_cn23xx_pf_reset_io_queues(oct))
256 reg_val = oct->pcie_port <<
261 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
272 iq = oct->instr_queue[q_no];
279 lio_read_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
283 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
291 lio_write_csr64(oct, inst_cnt_reg,
292 (lio_read_csr64(oct, inst_cnt_reg) &
302 lio_cn23xx_pf_setup_global_output_regs(struct octeon_device *oct)
304 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
308 srn = oct->sriov_info.pf_srn;
309 ern = srn + oct->sriov_info.num_pf_rings;
312 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 32);
315 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 0);
319 reg_val = lio_read_csr32(oct,
351 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(q_no),
355 * Enabling these interrupt in oct->fn_list.enable_interrupt()
361 oct, (uint32_t)LIO_GET_OQ_INTR_TIME_CFG(cn23xx->conf));
363 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no),
369 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 0x40);
372 if (oct->pf_num)
373 lio_write_csr64(oct, LIO_CN23XX_SLI_OUT_BP_EN2_W1S,
376 lio_write_csr64(oct, LIO_CN23XX_SLI_OUT_BP_EN_W1S,
381 lio_cn23xx_pf_setup_device_regs(struct octeon_device *oct)
384 lio_cn23xx_pf_enable_error_reporting(oct);
387 lio_cn23xx_pf_setup_global_mac_regs(oct);
389 if (lio_cn23xx_pf_setup_global_input_regs(oct))
392 lio_cn23xx_pf_setup_global_output_regs(oct);
398 lio_write_csr64(oct, LIO_CN23XX_SLI_WINDOW_CTL,
402 lio_write_csr64(oct, LIO_CN23XX_SLI_PKT_IN_JABBER,
408 lio_cn23xx_pf_setup_iq_regs(struct octeon_device *oct, uint32_t iq_no)
410 struct lio_instr_queue *iq = oct->instr_queue[iq_no];
413 iq_no += oct->sriov_info.pf_srn;
416 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_BASE_ADDR64(iq_no),
418 lio_write_csr32(oct, LIO_CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count);
426 lio_dev_dbg(oct, "InstQ[%d]:dbell reg @ 0x%x instcnt_reg @ 0x%x\n",
433 pkt_in_done = lio_read_csr64(oct, iq->inst_cnt_reg);
435 if (oct->msix_on) {
437 lio_write_csr64(oct, iq->inst_cnt_reg,
444 lio_write_csr64(oct, iq->inst_cnt_reg, pkt_in_done);
451 lio_cn23xx_pf_setup_oq_regs(struct octeon_device *oct, uint32_t oq_no)
453 struct lio_droq *droq = oct->droq[oq_no];
454 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
459 oq_no += oct->sriov_info.pf_srn;
461 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_BASE_ADDR64(oq_no),
463 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_SIZE(oq_no), droq->max_count);
465 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no),
472 if (!oct->msix_on) {
478 lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no));
480 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no),
488 lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no));
490 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no),
493 time_threshold = lio_cn23xx_pf_get_oq_ticks(oct,
497 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_PKT_INT_LEVELS(oq_no),
504 lio_cn23xx_pf_enable_io_queues(struct octeon_device *oct)
510 srn = oct->sriov_info.pf_srn;
511 ern = srn + oct->num_iqs;
515 if (oct->io_qmask.iq64B & BIT_ULL(q_no - srn)) {
516 reg_val = lio_read_csr64(oct,
519 lio_write_csr64(oct,
524 if (oct->io_qmask.iq & BIT_ULL(q_no - srn)) {
529 reg_val = lio_read_csr64(oct,
538 reg_val = lio_read_csr64(oct,
543 lio_dev_err(oct, "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
549 lio_write_csr64(oct,
553 reg_val = lio_read_csr64(oct,
556 lio_dev_err(oct, "clearing the reset failed for qno: %u\n",
561 reg_val = lio_read_csr64(oct,
564 lio_write_csr64(oct,
572 if (oct->io_qmask.oq & BIT_ULL(q_no - srn)) {
573 reg_val = lio_read_csr32(oct,
576 lio_write_csr32(oct,
585 lio_cn23xx_pf_disable_io_queues(struct octeon_device *oct)
593 srn = oct->sriov_info.pf_srn;
594 ern = srn + oct->num_iqs;
601 d64 = lio_read_csr64(oct,
605 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
612 d64 = lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_IOQ_RING_RST);
614 d64 = lio_read_csr64(oct,
621 lio_write_csr32(oct, LIO_CN23XX_SLI_IQ_DOORBELL(q_no),
623 while (((lio_read_csr64(oct,
639 d64 = lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_IOQ_RING_RST);
641 d64 = lio_read_csr64(oct,
648 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_CREDIT(q_no),
650 while ((lio_read_csr64(oct,
657 d32 = lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_SENT(q_no));
658 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_SENT(q_no), d32);
666 struct octeon_device *oct = ioq_vector->oct_dev;
667 struct lio_droq *droq = oct->droq[ioq_vector->droq_index];
672 lio_dev_err(oct, "23XX bringup FIXME: oct pfnum:%d ioq_vector->ioq_num :%d droq is NULL\n",
673 oct->pf_num, ioq_vector->ioq_num);
676 pkts_sent = lio_read_csr64(oct, droq->pkts_sent_reg);
704 struct octeon_device *oct = (struct octeon_device *)dev;
705 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
708 lio_dev_dbg(oct, "In %s octeon_dev @ %p\n", __func__, oct);
709 intr64 = lio_read_csr64(oct, cn23xx->intr_sum_reg64);
711 oct->int_status = 0;
714 lio_dev_err(oct, "Error Intr: 0x%016llx\n",
717 if (oct->msix_on != LIO_FLAG_MSIX_ENABLED) {
719 oct->int_status |= LIO_DEV_INTR_PKT_DATA;
723 oct->int_status |= LIO_DEV_INTR_DMA0_FORCE;
726 oct->int_status |= LIO_DEV_INTR_DMA1_FORCE;
729 lio_write_csr64(oct, cn23xx->intr_sum_reg64, intr64);
733 lio_cn23xx_pf_bar1_idx_setup(struct octeon_device *oct, uint64_t core_addr,
740 reg_adr = lio_pci_readq(oct,
741 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
744 lio_pci_writeq(oct, (bar1 & 0xFFFFFFFEULL),
745 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
747 reg_adr = lio_pci_readq(oct,
748 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
757 lio_pci_writeq(oct, (((core_addr >> 22) << 4) | LIO_PCI_BAR1_MASK),
758 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
760 bar1 = lio_pci_readq(oct, LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
765 lio_cn23xx_pf_bar1_idx_write(struct octeon_device *oct, uint32_t idx,
769 lio_pci_writeq(oct, mask,
770 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
774 lio_cn23xx_pf_bar1_idx_read(struct octeon_device *oct, uint32_t idx)
777 return ((uint32_t)lio_pci_readq(oct,
778 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port,
786 struct octeon_device *oct = iq->oct_dev;
789 uint32_t pkt_in_done = lio_read_csr32(oct, iq->inst_cnt_reg);
807 lio_cn23xx_pf_enable_interrupt(struct octeon_device *oct, uint8_t intr_flag)
809 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
815 lio_write_csr64(oct, cn23xx->intr_enb_reg64,
818 intr_val = lio_read_csr64(oct, cn23xx->intr_enb_reg64);
820 lio_write_csr64(oct, cn23xx->intr_enb_reg64, intr_val);
825 lio_cn23xx_pf_disable_interrupt(struct octeon_device *oct, uint8_t intr_flag)
827 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
832 lio_write_csr64(oct, cn23xx->intr_enb_reg64, 0);
834 intr_val = lio_read_csr64(oct, cn23xx->intr_enb_reg64);
836 lio_write_csr64(oct, cn23xx->intr_enb_reg64, intr_val);
841 lio_cn23xx_pf_get_pcie_qlmport(struct octeon_device *oct)
843 oct->pcie_port = (lio_read_csr32(oct,
846 lio_dev_dbg(oct, "CN23xx uses PCIE Port %d\n",
847 oct->pcie_port);
851 lio_cn23xx_pf_get_pf_num(struct octeon_device *oct)
856 fdl_bit = lio_read_pci_cfg(oct, LIO_CN23XX_PCIE_SRIOV_FDL);
857 oct->pf_num = ((fdl_bit >> LIO_CN23XX_PCIE_SRIOV_FDL_BIT_POS) &
862 lio_cn23xx_pf_setup_reg_address(struct octeon_device *oct)
864 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
866 oct->reg_list.pci_win_wr_addr = LIO_CN23XX_SLI_WIN_WR_ADDR64;
868 oct->reg_list.pci_win_rd_addr_hi = LIO_CN23XX_SLI_WIN_RD_ADDR_HI;
869 oct->reg_list.pci_win_rd_addr_lo = LIO_CN23XX_SLI_WIN_RD_ADDR64;
870 oct->reg_list.pci_win_rd_addr = LIO_CN23XX_SLI_WIN_RD_ADDR64;
872 oct->reg_list.pci_win_wr_data_hi = LIO_CN23XX_SLI_WIN_WR_DATA_HI;
873 oct->reg_list.pci_win_wr_data_lo = LIO_CN23XX_SLI_WIN_WR_DATA_LO;
874 oct->reg_list.pci_win_wr_data = LIO_CN23XX_SLI_WIN_WR_DATA64;
876 oct->reg_list.pci_win_rd_data = LIO_CN23XX_SLI_WIN_RD_DATA64;
878 lio_cn23xx_pf_get_pcie_qlmport(oct);
881 if (!oct->msix_on)
885 LIO_CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num);
887 LIO_CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num);
891 lio_cn23xx_pf_sriov_config(struct octeon_device *oct)
893 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip;
895 cn23xx->conf = (struct lio_config *)lio_get_config_info(oct, LIO_23XX);
899 if (oct->sriov_info.num_pf_rings) {
900 num_pf_rings = oct->sriov_info.num_pf_rings;
903 lio_dev_warn(oct, "num_queues_per_pf requested %u is more than available rings (%u). Reducing to %u\n",
904 oct->sriov_info.num_pf_rings,
917 oct->sriov_info.trs = total_rings;
918 oct->sriov_info.pf_srn = total_rings - num_pf_rings;
919 oct->sriov_info.num_pf_rings = num_pf_rings;
921 lio_dev_dbg(oct, "trs:%d pf_srn:%d num_pf_rings:%d\n",
922 oct->sriov_info.trs, oct->sriov_info.pf_srn,
923 oct->sriov_info.num_pf_rings);
929 lio_cn23xx_pf_setup_device(struct octeon_device *oct)
934 data32 = lio_read_pci_cfg(oct, 0x10);
936 data32 = lio_read_pci_cfg(oct, 0x14);
938 data32 = lio_read_pci_cfg(oct, 0x18);
940 data32 = lio_read_pci_cfg(oct, 0x1c);
945 lio_dev_err(oct, "Device BAR0 unassigned\n");
948 lio_dev_err(oct, "Device BAR1 unassigned\n");
953 if (lio_map_pci_barx(oct, 0))
956 if (lio_map_pci_barx(oct, 1)) {
957 lio_dev_err(oct, "%s CN23XX BAR1 map failed\n", __func__);
958 lio_unmap_pci_barx(oct, 0);
962 lio_cn23xx_pf_get_pf_num(oct);
964 if (lio_cn23xx_pf_sriov_config(oct)) {
965 lio_unmap_pci_barx(oct, 0);
966 lio_unmap_pci_barx(oct, 1);
969 lio_write_csr64(oct, LIO_CN23XX_SLI_MAC_CREDIT_CNT,
972 oct->fn_list.setup_iq_regs = lio_cn23xx_pf_setup_iq_regs;
973 oct->fn_list.setup_oq_regs = lio_cn23xx_pf_setup_oq_regs;
974 oct->fn_list.process_interrupt_regs = lio_cn23xx_pf_interrupt_handler;
975 oct->fn_list.msix_interrupt_handler =
978 oct->fn_list.soft_reset = lio_cn23xx_pf_soft_reset;
979 oct->fn_list.setup_device_regs = lio_cn23xx_pf_setup_device_regs;
980 oct->fn_list.update_iq_read_idx = lio_cn23xx_pf_update_read_index;
982 oct->fn_list.bar1_idx_setup = lio_cn23xx_pf_bar1_idx_setup;
983 oct->fn_list.bar1_idx_write = lio_cn23xx_pf_bar1_idx_write;
984 oct->fn_list.bar1_idx_read = lio_cn23xx_pf_bar1_idx_read;
986 oct->fn_list.enable_interrupt = lio_cn23xx_pf_enable_interrupt;
987 oct->fn_list.disable_interrupt = lio_cn23xx_pf_disable_interrupt;
989 oct->fn_list.enable_io_queues = lio_cn23xx_pf_enable_io_queues;
990 oct->fn_list.disable_io_queues = lio_cn23xx_pf_disable_io_queues;
992 lio_cn23xx_pf_setup_reg_address(oct);
994 oct->coproc_clock_rate = 1000000ULL *
995 lio_cn23xx_pf_coprocessor_clock(oct);
1001 lio_cn23xx_pf_fw_loaded(struct octeon_device *oct)
1005 val = lio_read_csr64(oct, LIO_CN23XX_SLI_SCRATCH2);