dev/ixl/if_ixlv.c

1446 	struct		tx_ring	 *txr;
1455 		txr = &que->txr;
1694 	struct tx_ring		*txr;
1699 	txr = &que->txr;
1700 	txr->que = que;
1701 	txr->tail = I40E_QTX_TAIL1(que->me);
1703 	snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)",
1705 	mtx_init(&txr->mtx, txr->mtx_name, NULL, MTX_DEF);
1722 	    &txr->dma, i40e_mem_reserved, tsize, DBA_ALIGN)) {
1728 	txr->base = (struct i40e_tx_desc *)txr->dma.va;
1729 	bzero((void *)txr->base, tsize);
1738 	txr->br = buf_ring_alloc(ixlv_txbrsz, M_DEVBUF,
1739 	    M_WAITOK, &txr->mtx);
1740 	if (txr->br == NULL) {
1786 	buf_ring_free(txr->br, M_DEVBUF);
1790 	i40e_free_dma_mem(&sc->hw, &txr->dma);
1792 	mtx_destroy(&txr->mtx);
2087 		struct tx_ring	*txr = &que->txr;
2097 		txr->itr = vsi->tx_itr_setting;
2098 		txr->latency = IXL_AVE_LATENCY;
2185 	struct tx_ring	*txr = &que->txr;
2192 	if (txr->bytes == 0)
2196 		tx_bytes = txr->bytes/txr->itr;
2197 		tx_itr = txr->itr;
2199 		switch (txr->latency) {
2223 		txr->latency = tx_latency;
2225 		if (tx_itr != txr->itr) {
2227 			tx_itr = (10 * tx_itr * txr->itr) /
2228 			    ((9 * tx_itr) + txr->itr);
2229 			txr->itr = min(tx_itr, IXL_MAX_ITR);
2231 			    que->me), txr->itr);
2238 		if (txr->itr != vsi->tx_itr_setting) {
2239 			txr->itr = vsi->tx_itr_setting;
2241 			    que->me), txr->itr);
2244 	txr->bytes = 0;
2245 	txr->packets = 0;
2261 	struct tx_ring  *txr = &que->txr;
2267 		mtx_lock(&txr->mtx);
2269 		if (!drbr_empty(ifp, txr->br))
2270 			ixl_mq_start_locked(ifp, txr);
2271 		mtx_unlock(&txr->mtx);
2295 	struct tx_ring	*txr = &que->txr;
2311 	mtx_lock(&txr->mtx);
2318 	if (!drbr_empty(vsi->ifp, txr->br))
2320 	mtx_unlock(&txr->mtx);
2676 	struct tx_ring *txr = &que->txr;
2679 	if (!mtx_initialized(&txr->mtx)) /* uninitialized */
2681 	IXL_TX_LOCK(txr);
2682 	if (txr->br)
2683 		buf_ring_free(txr->br, M_DEVBUF);
2685 	if (txr->base)
2686 		i40e_free_dma_mem(&sc->hw, &txr->dma);
2687 	IXL_TX_UNLOCK(txr);
2688 	IXL_TX_LOCK_DESTROY(txr);
3148 	val = rd32(que->vsi->hw, que->txr.tail);